Yan Zhu
Orcid: 0000-0002-8298-3244Affiliations:
- University of Macau, Analog and Mixed Signal VLSI Laboratory, Macao, China
According to our database1,
Yan Zhu
authored at least 106 papers
between 2008 and 2024.
Collaborative distances:
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Bibliography
2024
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R.
IEEE J. Solid State Circuits, March, 2024
6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC.
IEEE J. Solid State Circuits, December, 2023
A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator.
IEEE J. Solid State Circuits, December, 2023
A 0.016mm<sup>2</sup> Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 25MHz-BW 77.2dB-SNDR 2<sup>nd</sup>-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Single-Channel 70dB-SNDR 100MHz-BW 4<sup>th</sup>-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to Machine Learning Attacks and High Energy Efficiency.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations.
IEEE J. Solid State Circuits, 2022
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration.
IEEE J. Solid State Circuits, 2022
A low dropout regulator with PSR under -48dB up to 20GHz for a SARADC reference buffer.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
2021
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC.
IEEE J. Solid State Circuits, 2021
Int. J. Circuit Theory Appl., 2021
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4<sup>th</sup> Nyquist Zone in 1GS/s ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 79.1dB-SNDR 20MHz-BW 2<sup>nd</sup>-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER<sup>-6</sup>.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT.
IEEE Trans. Circuits Syst., 2020
A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration.
IEEE Trans. Circuits Syst., 2020
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps.
IEEE J. Solid State Circuits, 2020
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier.
IEEE J. Solid State Circuits, 2020
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 4-b 7-µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques.
IEEE J. Solid State Circuits, 2019
A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Input Correlated Swap-Sampling Technique for Input Driver Power Reduction in a 12b 25MS/s SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A 0.19 mm<sup>2</sup> 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 12b 180MS/s 0.068mm<sup>2</sup> With Full-Calibration-Integrated Pipelined-SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016
A 12b 180MS/s 0.068mm<sup>2</sup> pipelined-SAR ADC with merged-residue DAC for noise reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 0.011mm<sup>2</sup> 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the ESSCIRC 2014, 2014
2013
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation.
IEEE J. Solid State Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
VLSI Design, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE J. Solid State Circuits, 2010
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008