Junzhe Jing
Orcid: 0009-0009-5662-3366
According to our database1,
Junzhe Jing authored at least 2 papers
in 2026.
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Bibliography
2026
IEEE Comput. Archit. Lett., 2026
AsymVPU: A Scalable and Area-Efficient Vector Architecture via Intra-Lane Asymmetry and Hierarchical Co-Design.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026