Jürgen Schietke

According to our database1, Jürgen Schietke authored at least 4 papers between 1998 and 2002.

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Bibliography

2002
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip.
Discret. Appl. Math., 2002

2000
Platzierungsbasierte Logikoptimierung komplexer VLSI Chips.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

1999
Cycle time and slack optimization for VLSI-chips.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset.
Proceedings of the 1998 Design, 1998


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