Jyh-Ting Lai

According to our database, Jyh-Ting Lai authored at least 9 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme.

Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu

J. Signal Process. Syst., 2008

2007

A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems.

Jyh-Ting Lai, An-Yeu Wu, Wen-Chiang Chen

IEEE Trans. Veh. Technol., 2007

Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs.

Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee

IEEE Trans. Very Large Scale Integr. Syst., 2007

Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems.

Chun-Yuan Chu, Jyh-Ting Lai, An-Yeu Wu

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2006

A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems.

Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems.

Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2004

High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai

IEEE Trans. Very Large Scale Integr. Syst., 2004

Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique.

Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai

IEEE Trans. Circuits Syst. II Express Briefs, 2004

1000BASE-T Gigabit Ethernet baseband DSP IC design.

Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004