Jyotindra R. Shakya

According to our database, Jyotindra R. Shakya authored at least 7 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 16 GΩ Input Impedance Amplifier with Flicker Noise Reduction for Neural Recording Applications.

Jyotindra R. Shakya, Gabor C. Temes, Faraz Adin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2023

Mismatch Shaping for Binary-Coded DAC.

Jyotindra R. Shakya, Gabor C. Temes

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2020

Efficient Calibration of Feedback DAC in Delta Sigma Modulators.

Jyotindra R. Shakya, Gabor C. Temes

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Slewing Mitigation Technique for Switched Capacitor Circuits.

Manjunath Kareppagoudr, Jyotindra R. Shakya, Emanuel Caceres, Yu-Wen Kuo, Gabor C. Temes

IEEE Trans. Circuits Syst., 2020

Pseudo-Pseudo-Differential Multibit Delta-Sigma Modulator.

Emanuel Caceres, Manjunath Kareppagoudr, Jyotindra R. Shakya, Gabor C. Temes

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

Passive slew rate enhancement technique for Switched-Capacitor Circuits.

Manjunath Kareppagoudr, Emanuel Caceres, Yu-Wen Kuo, Jyotindra R. Shakya, Yanchao Wang, Gabor C. Temes

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Predictive Noise Shaping SAR ADC.

Jyotindra R. Shakya, Ajmal K. Vadakkan, Gabor C. Temes

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019