Manjunath Kareppagoudr

Orcid: 0000-0002-1634-0769

According to our database1, Manjunath Kareppagoudr authored at least 9 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Slewing Mitigation Technique for Switched Capacitor Circuits.
IEEE Trans. Circuits Syst., 2020

Pseudo-Pseudo-Differential Multibit Delta-Sigma Modulator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Passive slew rate enhancement technique for Switched-Capacitor Circuits.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
Pseudo-pseudo-differential circuits.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017


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