Jyotindra R. Shakya

Orcid: 0000-0001-7640-3939

According to our database1, Jyotindra R. Shakya authored at least 6 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Mismatch Shaping for Binary-Coded DAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2020
Efficient Calibration of Feedback DAC in Delta Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Slewing Mitigation Technique for Switched Capacitor Circuits.
IEEE Trans. Circuits Syst., 2020

Pseudo-Pseudo-Differential Multibit Delta-Sigma Modulator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Passive slew rate enhancement technique for Switched-Capacitor Circuits.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Predictive Noise Shaping SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019


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