Kaiyun Cao
Orcid: 0009-0008-5372-1756Timeline
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Bibliography
2025
An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving -251.9 dB FOM<sub>Jitter-N</sub>.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025
A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025