Liangjian Lyu
Orcid: 0000-0002-6157-0109
According to our database1,
Liangjian Lyu
authored at least 17 papers
between 2018 and 2023.
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Bibliography
2023
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Microscopic Characterization of Failure Mechanisms in Long-Term Implanted Microwire Neural Electrodes.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Sensors, 2022
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2020
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation.
IEEE J. Solid State Circuits, 2020
Integr., 2020
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018