Liangjian Lyu
Orcid: 0000-0002-6157-0109
According to our database1,
Liangjian Lyu authored at least 33 papers
between 2018 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A 1ppm/°C and ±0.066% 3σ Accuracy Bandgap Reference with Temperature-Adaptive PTAT Scaling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A Neural Spike Sorting Framework with Multi-Scale Slope Detection and Lite-CNN Classification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
An Injection-Locked Eight Phase Clock Generator with Edge Replacement and Injection Error Calibration Achieving -253.7dB FOMJitter-N.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A Miniaturized Wireless Multimodal Physiological In-Vivo Monitoring Platform Featuring Power-Efficient Photoelectrochemical Sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A 256-Channel, 3.49-mW Wireless Neural Recording SoC with Adaptive Delta Compression and Error-Resilient Coding.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving -251.9 dB FOM<sub>Jitter-N</sub>.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025
A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity.
IEEE J. Solid State Circuits, March, 2025
A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 0.473 μJ/class Seizure Detection Processor with LSVM Classifier and LPF-Based Feature Extraction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 40µW 915MHz Receiver with Sub-Passive Third-Harmonic Mixer Achieving -88dBm Sensitivity and Multi-Channel Selection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Microscopic Characterization of Failure Mechanisms in Long-Term Implanted Microwire Neural Electrodes.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Sensors, 2022
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2020
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation.
IEEE J. Solid State Circuits, 2020
Integr., 2020
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018