Kazuhito Tsutsumi

According to our database, Kazuhito Tsutsumi authored at least 3 papers between 1990 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell.

Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

1991

A 21-mW 4-Mb CMOS SRAM for battery operation.

Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami

IEEE J. Solid State Circuits, November, 1991

1990

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture.

Toshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa Nishimura, Yoshio Kohno, Kenji Anami

IEEE J. Solid State Circuits, October, 1990