Hirotoshi Sato

According to our database, Hirotoshi Sato authored at least 6 papers between 1996 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Application of tablet devices with digitizer pens in a chemical presentation course at college of technology.

Hirotoshi Sato, Kozo Fukumoto, Aiko Oshio

Proceedings of the IEEE/SICE International Symposium on System Integration, 2017

2016

Application of tablet devices in a chemical laboratory at college of technology.

Hirotoshi Sato, Kozo Fukumoto, Aiko Oshio

Proceedings of the 2016 IEEE/SICE International Symposium on System Integration, 2016

2014

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.

Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato

Proceedings of the Symposium on VLSI Circuits, 2014

1999

A 500-MHz pipelined burst SRAM with improved SER immunity.

Hirotoshi Sato, Tomohisa Wada, Shigeki Ohbayashi, Kunihiko Kozaru, Yasuyuki Okamoto, Yoshiko Higashide, Tadayuki Shimizu, Yukio Maki, Rui Morimoto, Hisakazu Otoi, Tsuyoshi Koga, Hiroki Honda, Makoto Taniguchi, Yutaka Arita, Toru Shiomi

IEEE J. Solid State Circuits, 1999

1998

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell.

Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

1996

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond.

Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami

IEEE J. Solid State Circuits, 1996