Ke Wu

Orcid: 0000-0002-0190-3725

Affiliations:

Shanghai Jiao Tong University, Shanghai, China

According to our database¹, Ke Wu authored at least 5 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2025

A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

2023

A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021

An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Ke Wu

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Bibliography

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