Jianjun Zhou
Orcid: 0000-0001-9898-7285Affiliations:
- Shanghai Jiao Tong University, Shanghai, China
According to our database1,
Jianjun Zhou authored at least 86 papers
between 1998 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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on orcid.org
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Bibliography
2026
A 40-nm CMOS Phase-Tunable Four-Phase Injection-Locked Ring VCO Utilizing Unbalanced Feedforward Topology Achieving -211.1- to -207.3-dBc/Hz FoM<sub>A</sub> Over Differential/Orthogonal Phase Range of -90.0° to 80.9°/-69.6° to 76.5°.
IEEE J. Solid State Circuits, May, 2026
A 37-48 GHz Frequency Doubler With >47.8 dBc FRR Utilizing a Staggered Fundamental Suppression Technique.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2026
IEEE Trans. Circuits Syst. II Express Briefs, March, 2026
IEEE Trans. Circuits Syst. II Express Briefs, February, 2026
A 3-5 V to Sub-1 V DLDO-SC-Sigma Converter With Auxiliary Loop for Efficiency Improvement in High-Density Power Delivery.
IEEE J. Solid State Circuits, February, 2026
A 14-bit 1.4 GS/s current-steering DAC with square-dithered frequency-modulated DEM achieving >60-dBc SFDR in 180 nm CMOS.
Microelectron. J., 2026
An energy-efficient 128 Gb/s PAM-4 wireline transmitter with a passive 4:1 MUX in 22 nm CMOS.
Microelectron. J., 2026
A 0.69-pJ/bit 16/24/32-Gb/s/pin NRZ/PAM-3/PAM-4 Multi-Mode Transmitter with Power-Optimal Rx Termination and Clock-Embedded DBI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A 5-to-1V DLDO-Hybrid-Sigma Converter Achieving Fast Transient for High-Density Power Delivery.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
2025
A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
A 470 μW 20 kHz-BW 107.3 dB-SNDR Nested CT DSM Using Negative-R-Based Cross-RC Integrator and Weighted Multi-Threshold MSB-Pass Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
A Reference Oversampling PLL With a FoM<sub>REF</sub> of -240.1 dB Enabled By a Capacitive Parasitic-Proof Ring Oscillator and a Time-Multiplexed Gm Stage.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
Microelectron. J., 2025
A reconfigurable passive LNA using an N-path switched-capacitor transformer with 2×/3× voltage Gain.
Microelectron. J., 2025
A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS.
Microelectron. J., September, 2023
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization.
IEEE J. Solid State Circuits, September, 2023
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.
IEEE J. Solid State Circuits, February, 2023
A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., November, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 0.023-12 GHz ultra-wideband frequency synthesizer with FOM<sub><i>T</i></sub> of -251.8 dB.
Microelectron. J., 2022
Circuits Syst. Signal Process., 2022
A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS.
Microelectron. J., 2021
A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction.
Microelectron. J., 2021
An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications.
Microelectron. J., 2021
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS.
Circuits Syst. Signal Process., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance.
IEEE Trans. Circuits Syst., 2020
A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
2018
Microelectron. J., 2018
IET Circuits Devices Syst., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IET Circuits Devices Syst., 2016
2015
IEICE Electron. Express, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEICE Electron. Express, 2014
IEICE Electron. Express, 2014
IEICE Electron. Express, 2014
Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
All-Digital Adaptive Module for Automatic Background IIP2 Calibration in CMOS Downconverters With Fast Convergence.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Adaptive calibration of IIP2 in direct down-conversion mixers with modified LMS algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
1998
Monolithic transformers and their application in a differential CMOS RF low-noise amplifier.
IEEE J. Solid State Circuits, 1998