Keitaro Sekine

According to our database, Keitaro Sekine authored at least 21 papers between 1999 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A Signal Detection Circuit for 8b/10b 2.5 Gb/s Serial Data Communication System in 90 nm CMOS.

Kozue Sasaki, Hiroki Sato, Akira Hyogo, Keitaro Sekine

IEICE Trans. Electron., 2010

2008

Input-Feedforward Two-Path Band-Pass Delta-Sigma Modulator Based on Horizontal or Vertical Opamp Sharing Technique.

Naoya Waki, Hiroki Sato, Akira Hyogo, Keitaro Sekine

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Balanced Three-Phase Active-RC Tow-Thomas Biquad Complex Filter for Wireless Communication Systems.

Junya Matsuno, Hiroki Sato, Akira Hyogo, Keitaro Sekine

IEICE Trans. Electron., 2008

A 5Gb/s adaptive equalizer using filter switching.

Tsutomu Tomioka, Takahiro Fujita, Kozue Sasaki, Hiroki Sato, Akira Hyogo, Keitaro Sekine

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Signal-to-noise ratio improvement of common-gate CMOS LNA for Ultra-Wide-Band.

Teppei Hayashi, Hiroki Sato, Akira Hyogo, Keitaro Sekine

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A High Impedance Current Source Using Active Resistor.

Takeshi Koike, Hiroki Sato, Akira Hyogo, Keitaro Sekine

IEICE Trans. Electron., 2007

2006

A Design Approach for Low Phase Noise 5GHz Complementary Quadrature Oscillator.

Yukio Hattori, Hiroki Sato, Akira Hyogo, Keitaro Sekine

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

A low voltage OTA using MOSFET in the triode region and cascode current mirror.

Hiroki Sato, Akira Hyogo, Keitaro Sekine

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A 2.0-V folding circuit using current limiting amplifier for ADC.

Takeshi Koike, Akira Hyogo, Keitaro Sekine

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2003

An Equivalent MOSFET Cell Using Adaptively Biased Source-Coupled Pair.

Hiroki Sato, Akira Hyogo, Keitaro Sekine

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A CMOS Current-Mode Band-Pass Filter Using <i>Q</i>-Enhancement Technique.

Yuhki Maruyama, Akira Hyogo, Keitaro Sekine

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A 1.8-V 73-dB dynamic-range CMOS variable gain amplifier.

Ryutaro Saito, Kinya Hosoda, Akira Hyogo, Takaya Maruyama, Hiroshi Komuraki, Hisayasu Sato, Keitaro Sekine

Proceedings of the ESSCIRC 2003, 2003

2002

Foreword.

Keitaro Sekine

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A Digitally Programmable CMOS Universal Biquad Filter Using Current-Mode Integrators.

Yuhki Maruyama, Akira Hyogo, Keitaro Sekine

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2.4-GHz-Band CMOS RF Front-End Building Blocks at a 1.8-V Supply.

Hiroshi Komurasaki, Kazuya Yamamoto, Hideyuki Wakada, Tetsuya Heima, Akihiko Furukawa, Hisayasu Sato, Takahiro Miki, Naoyuki Kato, Akira Hyogo, Keitaro Sekine

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A V_t-zero equivalent MOSFET and its applications.

Hiroki Sato, Akira Hyogo, Keitaro Sekine

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Experiences on an Open Source Translation Effort in Japan.

Hiroki Sato, Keitaro Sekine

Proceedings of BSDCon 2002, San Francisco, California, USA, February 11-14, 2002, 2002

Low-power ASK receiver circuit for wireless communication system.

Toru Yazaki, Hiroya Yamamoto, Akira Hyogo, Keitaro Sekine

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

A CMOS OTA free from second order effects with a high input resistance Gm control terminal.

Eitake Ibaragi, Soushirou Nishioka, Akira Hyogo, Keitaro Sekine

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A 1-MHz 7th-order continuous-time lowpass filter using very low distortion CMOS OTAs.

Eitake Ibaragi, Akira Hyogo, Keitaro Sekine

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair.

Akira Hyogo, Y. Fukutomi, Keitaro Sekine

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999