Kent D. Layton

According to our database1, Kent D. Layton authored at least 4 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 0.2-V 10-bit 5-kHz SAR ADC with Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A 9-Bit 10-MHz 28-µW SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2008
Bulk-driven gain-enhanced fully-differential amplifier for VT + 2Vdsat operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2004
A programmable floating-gate voltage reference in 0.5 μm CMOS.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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