Kent D. Layton

According to our database, Kent D. Layton authored at least 5 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 0.2-V 10-Bit 5-kHz SAR ADC With Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator.

Alexander Petrie, Yixin Song, Whitney Kinnison, Yong Qu, Kent D. Layton, Shiuh-Hua Wood Chiang

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

2020

A 0.2-V 10-bit 5-kHz SAR ADC with Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator.

Alexander Petrie, Whitney Kinnison, Yixin Song, Shiuh-Hua Wood Chiang, Kent D. Layton

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

A 9-Bit 10-MHz 28-µW SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC.

Devon Janke, Andrew Monk, Eric Swindlehurst, Kent D. Layton, Shiuh-Hua Wood Chiang

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2008

Bulk-driven gain-enhanced fully-differential amplifier for VT + 2Vdsat operation.

Kent D. Layton, Donald T. Comer, David J. Comer

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2004

A programmable floating-gate voltage reference in 0.5 μm CMOS.

Seth A. Cook, Kent D. Layton, William J. Marble, Donald T. Comer, David J. Comer, Craig S. Petrie

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004