Kgj Vishnu

According to our database, Kgj Vishnu authored at least 1 paper in 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology.

Subhadeep Datta, Arnab Banerjee, Ayush Tripathi, Dongmin Kang, Leesunghyuck, Hasung Lim, Wonsik Yu, Kgj Vishnu, Chanyoung Jeong, Sumanth Chakkirala, Avneesh Singh Verma, Sachin Kashyap, Eg Jeevarathinam, Sunil Kumar Pandey, Jongjae Ryu, Sanjeeb Kumar Ghosh

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024