Wonsik Yu

According to our database1, Wonsik Yu authored at least 10 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2015
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter.
IEEE J. Solid State Circuits, 2015

2014
A 148fs<sub>rms</sub> Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register.
IEEE J. Solid State Circuits, 2014

2013
A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier.
IEEE J. Solid State Circuits, 2013

A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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