Sanjeeb Kumar Ghosh

According to our database, Sanjeeb Kumar Ghosh authored at least 3 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface.

Hari Vijay Venkatanarayanan, Rustum Prasad Sahu, Maheswara Alamuru, Ergam Reddy Battini, Syed Mohammed Haroon, Saurav Suman, Deepika Mallela, Sanjeeb Kumar Ghosh, Billy Koo

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024

A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology.

Subhadeep Datta, Arnab Banerjee, Ayush Tripathi, Dongmin Kang, Leesunghyuck, Hasung Lim, Wonsik Yu, Kgj Vishnu, Chanyoung Jeong, Sumanth Chakkirala, Avneesh Singh Verma, Sachin Kashyap, Eg Jeevarathinam, Sunil Kumar Pandey, Jongjae Ryu, Sanjeeb Kumar Ghosh

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2020

A 2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPort Version1.4b to Support 14dB Channel Loss.

Gunjan Mandal, Sunil Rajan, Sanjeeb Kumar Ghosh, Saikat Hazra, Raghavendra Molthati, Parin Rajnikant Bhuta, Santosh Kumar Reddy, Vishnu Kalyanamahadevi Gopalan Jawarlal, Sumanth Chakkirala, Avneesh Singh Verma, Umamaheswara Reddy Katta, Venugopal Sadana, Dayakar Bethi, Abul Hassan Savanur, Praveen S. Bharadwaj, Krupal Jitendra Mehta, Kuntal Pandya

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020