Khyamling Parane

According to our database1, Khyamling Parane authored at least 10 papers between 2018 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of six.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA.
Wirel. Pers. Commun., 2020

LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA.
ACM Trans. Design Autom. Electr. Syst., 2020

An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks.
Circuits Syst. Signal Process., 2020

2019
Analysis of cache behaviour and software optimizations for faster on-chip network simulations.
Int. J. Syst. Assur. Eng. Manag., 2019

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs.
J. Circuits Syst. Comput., 2019

High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018


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