Ki-Wook Kim

Orcid: 0000-0002-7636-8990

According to our database1, Ki-Wook Kim authored at least 34 papers between 1996 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
ScienceIoT: Evolution of the Wireless Infrastructure of KREONET.
Sensors, 2021

2018
In-Network Data Processing in Software-Defined IoT with a Programmable Data Plane.
Mob. Inf. Syst., 2018

2017
An Authentication and Key Management Mechanism for Resource Constrained Devices in IEEE 802.11-based IoT Access Networks.
Sensors, 2017

A programmable data plane to support in-network data processing in software-defined IoT.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2017

2009
Distributed cluster head election algorithm using local energy estimation.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

2004
Coupling-aware high-level interconnect synthesis [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Energy-efficient skewed static logic with dual Vt: design and synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst., 2003

Chip-level charged-device modeling and simulation in CMOS integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002
Noise constrained transistor sizing and power optimization for dual Vs<sub>t</sub> domino logic.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst., 2002

Domino logic synthesis based on implication graph.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Optimal Timing for Skew-Tolerant High-Speed Domino Logic.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Coupling-aware high-level interconnect synthesis for low power.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
Proceedings of the 2002 Design, 2002

VeriCDF: a new verification methodology for charged device failures.
Proceedings of the 39th Design Automation Conference, 2002

Low-swing clock domino logic incorporating dual supply and dual threshold voltages.
Proceedings of the 39th Design Automation Conference, 2002

2001
Reliable Low -Power Solution for High -Performance VLSI Circuit Design
PhD thesis, 2001

Crosstalk noise minimization in domino logic design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Energy-efficient skewed static logic design with dual Vt.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Coupling-aware minimum delay optimization for domino logic circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Skew-tolerant high-speed (STHS) domino logic.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Noise constrained power optimization for dual VT domino logic.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
Proceedings of the 38th Design Automation Conference, 2001

2000
Noise-aware power optimization for on-chip interconnect.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Domino logic synthesis minimizing crosstalk.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Implication graph based domino logic synthesis.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Logic Transformation for Low Power Synthesis.
Proceedings of the 1999 Design, 1999

1996
VIRON: An Annotation-Based Video Information Retrieval System.
Proceedings of the COMPSAC '96, 1996


  Loading...