Kishore K. Duganapalli

According to our database, Kishore K. Duganapalli authored at least 9 papers between 2005 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Modelling and Test Generation for Crosstalk Faults in DSM Chips (Modellierung und Testfallgenerierung für Übersprechenfehler in DSM Chips)

Kishore K. Duganapalli

PhD thesis, 2016

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim.

Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier

J. Circuits Syst. Comput., 2016

2015

TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms.

Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2008

Crosstalk fault modeling in defective pair of interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Integr., 2008

2007

Parametric Yield Analysis of Mems via Statistical Methods

Shyam Praveen Vudathu, Kishore K. Duganapalli, Rainer Laur, D. Kubalinska, Angelika Bunse-Gerstner

CoRR, 2007

XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Modeling of Crosstalk Fault in Defective Interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.

Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.

Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005