Jürgen Schlöffel

According to our database, Jürgen Schlöffel authored at least 32 papers between 2000 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.

Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel

IEEE J. Solid State Circuits, 2017

2016

IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system.

Jean Durupt, Pascal Vivet, Juergen Schloeffel

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

3D DFT Challenges and Solutions.

Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Cell-Aware Test.

Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures.

Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Cell-aware experiences in a high-quality automotive test suite.

Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski

Proceedings of the 19th IEEE European Test Symposium, 2014

2012

Cell-aware Production test results from a 32-nm notebook processor.

Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski

Proceedings of the 2012 IEEE International Test Conference, 2012

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates.

Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Cell-aware analysis for small-delay effects and production test results from different fault models.

Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.

Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler

J. Electron. Test., 2010

Defect-oriented cell-internal testing.

Friedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger

Proceedings of the 2011 IEEE International Test Conference, 2010

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.

Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler

Proceedings of the 15th European Test Symposium, 2010

2009

SUPERB: Simulator utilizing parallel evaluation of resistive bridges.

Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian

ACM Trans. Design Autom. Electr. Syst., 2009

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille

it Inf. Technol., 2009

Restrict Encoding for Mixed-Mode BIST.

Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs.

Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

On Acceleration of SAT-Based ATPG for Industrial Designs.

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Resistive Bridging Fault Simulation of Industrial Circuits.

Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Deterministic logic BIST for transition fault testing.

Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers

IET Comput. Digit. Tech., 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Programmable deterministic Built-In Self-Test.

Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef

Proceedings of the 2007 IEEE International Test Conference, 2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults.

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Synthesis of irregular combinational functions with large don't care sets.

Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Computation and Application of Absolute Dominators in Industrial Designs.

Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel

Proceedings of the 12th European Test Symposium, 2007

2006

X-masking during logic BIST and its impact on defect coverage.

Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke

IEEE Trans. Very Large Scale Integr. Syst., 2006

Fault detection and diagnosis with parity trees for space compaction of test responses.

Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke

Proceedings of the 43rd Design Automation Conference, 2006

2005

Implementing a Scheme for External Deterministic Self-Test.

Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips.

Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.

Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.

Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2000

PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.

Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel

Proceedings of the Integrated Circuit Design, 2000