Koichi Wada

Orcid: 0000-0001-9271-5641

Affiliations:
  • University of Tsukuba, Japan


According to our database1, Koichi Wada authored at least 38 papers between 1987 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
Toward Parallelization Technique for Stream-based Lossless Data Compression.
Proceedings of the IEEE International Conference on Big Data, 2023

2022
Heuristic Method for Minimizing Model Size of CNN by Combining Multiple Pruning Techniques.
Sensors, 2022

2016
Performance Evaluation of Parallelizing Algorithm Using Spanning Tree for Stream-Based Computing.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015
Development of an Algorithm for Extracting Parallelism and Pipeline Structure from Stream-based Processing flow with Spanning Tree.
Int. J. Netw. Comput., 2015

2014
Parallelism Extraction Algorithm from Stream-Based Processing Flow Applying Spanning Tree.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
Probabilistic Analysis of Parallel Program with Partially Eliminated Barriers.
Proceedings of the 12th IEEE International Conference on Trust, 2013

Probabilistic Analysis of Barrier Eliminating Method Applied to Load-Imbalanced Parallel Application.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

Operation Synchronization Technique on Pipeline-Based Hardware Synthesis Applying Stream-Based Computing Framework.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2011
Communication latency tolerant parallel algorithm for particle swarm optimization.
Parallel Comput., 2011

Performance impact on resource sharing among multiple CPU- and GPU-based applications.
Int. J. Parallel Emergent Distributed Syst., 2011

A Uniform Platform to Support Multigenerational GPUs for High Performance Stream-based Computing.
Int. J. Netw. Comput., 2011

Probabilistic analysis of time reduction by eliminating barriers in parallel programmes.
Int. J. Commun. Networks Distributed Syst., 2011

Elimination Techniques of Redundant Data Transfers Among GPUs and CPU on Recursive Stream-Based Applications.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Improving Stream Buffer Management of Stream-Based Computing Platform on GPU.
Proceedings of the Second International Conference on Networking and Computing, 2011

2010
Design and Implementation of a Uniform Platform to Support Multigenerational GPU Architectures for High Performance Stream-Based Computing.
Proceedings of the First International Conference on Networking and Computing, 2010

2009
Performance study of interference on GPU and CPU resources with multiple applications.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

2007
Performance evaluation of offloading software modules to cluster network.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

2006
Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer.
J. Interconnect. Networks, 2006

Barrier Elimination Based on Access Dependency Analysis for OpenMP.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Architecture and Performance of Dynamic Offloader for Cluster Network.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

2005
Performance Enhancement of Inter-Cluster Communication with Software-based Data Compression Link Layer.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Quaver: OpenMP Compiler for Clusters based on Array Section Descriptor.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

High Performance Message Passing Library for Maestro2 Cluster Network.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

Active Zero-copy: A performance study of non-deterministic messaging.
Proceedings of the 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 2005

Image Interpolation using Feedforward Neural Network.
Proceedings of the IASTED International Conference on Artificial Intelligence and Applications, 2005

2004
Distributed Shared Memory System Based on the Maestro2 High Performance Cluster Network.
Proceedings of the 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 2004

On the performance of Maestro2 high performance network equipment, using new improvement techniques.
Proceedings of the 23rd IEEE International Performance Computing and Communications Conference, 2004

2002
On a Fluency Image Coding System for Beef Marbling Evaluation.
Pattern Recognit. Lett., 2002

High Performance Network of PC Cluster Maestro.
Clust. Comput., 2002

A Method on Tracking Unit Pixel Width Line Segments for Function Approximation-Based Image Coding.
Proceedings of the Advances in Multimedia Information Processing, 2002

2000
An approximation of data points by piecewise polynomial functions and their dual orthogonal functions.
Signal Process., 2000

Efficient event communication algorithm and its evaluation for parallel logic simulation.
Syst. Comput. Jpn., 2000

On a grading system for beef marbling.
Pattern Recognit. Lett., 2000

Design and Performance of Maestro Cluster Network.
Proceedings of the 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th, 2000

1998
PaRM: A parallel relaxation machine for handwritten character recognition.
Pattern Recognit. Lett., 1998

Maestro-Link: A High Performance Interconnect for PC Cluster.
Proceedings of the Field-Programmable Logic and Applications, 1998

1987
A Hardware Syntactic Analysis Processor.
IEEE Micro, 1987


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