Leonel Sousa
Orcid: 0000-0002-8066-221XAffiliations:
- University of Lisbon, Instituto Superior Tecnico, INESC-ID, Portugal
According to our database1,
Leonel Sousa
authored at least 322 papers
between 1997 and 2024.
Collaborative distances:
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Bibliography
2024
ACM Comput. Surv., March, 2024
2023
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
Special issue: 20th international workshop on algorithms, models and tools for parallel computing on heterogeneous platforms (HeteroPar'22).
Concurr. Comput. Pract. Exp., 2023
Proceedings of the High Performance Computing, 2023
Social and Environmental Effects of Post-COVID-19 Computer Science Virtual Conferencing: The Euro-Par Case.
Proceedings of the International Conference on ICT for Sustainability, 2023
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023
Proceedings of the Euro-Par 2023: Parallel Processing Workshops - Euro-Par 2023 International Workshops, Limassol, Cyprus, August 28, 2023
Proceedings of the Euro-Par 2023: Parallel Processing Workshops - Euro-Par 2023 International Workshops, Limassol, Cyprus, August 28, 2023
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2023
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
2022
J. Signal Process. Syst., 2022
ACM Trans. Reconfigurable Technol. Syst., 2022
J. Supercomput., 2022
Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic.
IEEE Trans. Emerg. Top. Comput., 2022
Inter-Algorithm Multiobjective Cooperation for Phylogenetic Reconstruction on Amino Acid Data.
IEEE Trans. Cybern., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Modeling and evaluation of dispatching policies in IaaS cloud data centers using SANs.
Sustain. Comput. Informatics Syst., 2022
Uncertainty Estimation via Monte Carlo Dropout in CNN-Based mmWave MIMO Localization.
IEEE Signal Process. Lett., 2022
Exploiting multi-level parallel metaheuristics and heterogeneous computing to boost phylogenetics.
Future Gener. Comput. Syst., 2022
Unlocking Personalized Healthcare on Modern CPUs/GPUs: Three-way Gene Interaction Study.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the 51st International Conference on Parallel Processing, 2022
Proceedings of the Approximate Computing, 2022
2021
Modeling Epidemic Routing: Capturing Frequently Visited Locations While Preserving Scalability.
IEEE Trans. Veh. Technol., 2021
IEEE Trans. Parallel Distributed Syst., 2021
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
Editorial on the Special Section on Algorithms, Circuits, and Systems for Signal Processing at the Edge.
IEEE Open J. Circuits Syst., 2021
Supporting RISC-V Performance Counters through Performance analysis tools for Linux (Perf).
CoRR, 2021
Comput. Electr. Eng., 2021
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021
Number Theoretic Transform Architecture suitable to Lattice-based Fully-Homomorphic Encryption.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
Modeling and Evaluation of Service Composition in Commercial Multiclouds Using Timed Colored Petri Nets.
IEEE Trans. Syst. Man Cybern. Syst., 2020
J. Supercomput., 2020
IEEE Trans. Inf. Forensics Secur., 2020
IEEE Trans. Computers, 2020
Neural Process. Lett., 2020
J. Real Time Image Process., 2020
J. Comput. Sci., 2020
IET Comput. Digit. Tech., 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
IEEE Des. Test, 2020
Performance Modeling of Epidemic Routing in Mobile Social Networks with Emphasis on Scalability.
CoRR, 2020
A hybrid algorithm for task scheduling on heterogeneous multiprocessor embedded systems.
Appl. Soft Comput., 2020
The Role of Non-Positional Arithmetic on Efficient Emerging Cryptographic Algorithms.
IEEE Access, 2020
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020
Proceedings of the 17th International Joint Conference on e-Business and Telecommunications, 2020
Proceedings of the Euro-Par 2020: Parallel Processing, 2020
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020
2019
J. Signal Process. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Modeling Non-Uniform Memory Access on Large Compute Nodes with the Cache-Aware Roofline Model.
IEEE Trans. Parallel Distributed Syst., 2019
Comparative assessment of GPGPU technologies to accelerate objective functions: A case study on parsimony.
J. Parallel Distributed Comput., 2019
A multiobjective adaptive approach for the inference of evolutionary relationships in protein-based scenarios.
Inf. Sci., 2019
IET Circuits Devices Syst., 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Future Gener. Comput. Syst., 2019
On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2n+k, 2n - 1, 2n+1 - 1}.
Comput. J., 2019
Scalable Performance Analysis of Epidemic Routing Considering Skewed Location Visiting Preferences.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019
Enhancing Beamformed Fingerprint Outdoor Positioning with Hierarchical Convolutional Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the Hybrid Artificial Intelligent Systems - 14th International Conference, 2019
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
Multiobjective Frog-Leaping Optimization for the Study of Ancestral Relationships in Protein Data.
IEEE Trans. Evol. Comput., 2018
Signal Process. Image Commun., 2018
Temperature-aware dynamic voltage and frequency scaling enabled MPSoC modeling using Stochastic Activity Networks.
Microprocess. Microsystems, 2018
ACM Comput. Surv., 2018
Proceedings of the 88th IEEE Vehicular Technology Conference, 2018
Proceedings of the High Performance Computing, 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 6th International Workshop on Parallelism in Bioinformatics, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 International Conference on Biomedical Engineering and Applications, 2018
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Phylogenetic Reconstructions Using an Indicator-Based Bat Algorithm for Multicore Processors.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2018
Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 2018
2017
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2<sup>k</sup>, 2<sup>P</sup>-1}.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Multim., 2017
A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2<sup>n</sup> + 1 Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices.
IEEE Trans. Computers, 2017
Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores.
IEEE Trans. Computers, 2017
Special issue on real-time energy-aware circuits and systems for HEVC and for its 3D and SVC extensions.
J. Real Time Image Process., 2017
Inf. Sci., 2017
IACR Cryptol. ePrint Arch., 2017
Sign Detection and Number Comparison on RNS 3-Moduli Sets \(\{2^n-1, 2^{n+x}, 2^n+1\}\).
Circuits Syst. Signal Process., 2017
Concurr. Comput. Pract. Exp., 2017
Concurr. Comput. Pract. Exp., 2017
IEEE Access, 2017
IEEE Access, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model.
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, 2017
Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Efficient Reductions in Cyclotomic Rings - Application to Ring-LWE Based FHE Schemes.
Proceedings of the Selected Areas in Cryptography - SAC 2017, 2017
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017
Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017
2016
IEEE Trans. Circuits Syst. Video Technol., 2016
A Framework for Application-Guided Task Management on Heterogeneous Embedded Systems.
ACM Trans. Archit. Code Optim., 2016
Exploiting task and data parallelism for advanced video coding on hybrid CPU + GPU platforms.
J. Real Time Image Process., 2016
Integr., 2016
Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016
Proceedings of the 18th IEEE International Workshop on Multimedia Signal Processing, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Proceedings of the Information Security and Cryptology - ICISC 2016 - 19th International Conference, Seoul, South Korea, November 30, 2016
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016
2015
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Arithmetic-Based Binary-to-RNS Converter Modulo {2<sup>n</sup>±k} for jn-bit Dynamic Range.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
J. Real Time Image Process., 2015
Proceedings of the 12th International Workshop on Intelligent Solutions in Embedded Systems, 2015
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 IEEE International Symposium on Multimedia, 2015
Proceedings of the 2015 IEEE International Symposium on Multimedia, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
2014
J. Signal Process. Syst., 2014
J. Signal Process. Syst., 2014
Dynamic Load Balancing for Real-Time Video Encoding on Heterogeneous CPU+GPU Systems.
IEEE Trans. Multim., 2014
J. Circuits Syst. Comput., 2014
EURASIP J. Adv. Signal Process., 2014
Circuits Syst. Signal Process., 2014
On the Evaluation of Multi-core Systems with SIMD Engines for Public-Key Cryptography.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014
ROM-less RNS-to-binary converter moduli {2<sup>2n</sup> - 1, 2<sup>2n</sup> + 1, 2<sup>n</sup> - 3, 2<sup>n</sup> + 3}.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 43rd International Conference on Parallel Processing, 2014
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Cooperative CPU+GPU deblocking filter parallelization for high performance HEVC video codecs.
Proceedings of the IEEE International Conference on Acoustics, 2014
Opencl parallelization of the HEVC de-quantization and inverse transform for heterogeneous platforms.
Proceedings of the 22nd European Signal Processing Conference, 2014
Nonlinear system identification using constellation based multiple model adaptive estimators.
Proceedings of the 22nd European Signal Processing Conference, 2014
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014
Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Proceedings of the Numerical Computations with GPUs, 2014
2013
On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst., 2013
A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems.
IEEE Trans. Educ., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
The CRNS framework and its application to programmable and reconfigurable cryptography.
ACM Trans. Archit. Code Optim., 2013
Int. J. Parallel Program., 2013
Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.
IET Circuits Devices Syst., 2013
Monitoring Performance and Power for Application Characterization with the Cache-Aware Roofline Model.
Proceedings of the Parallel Processing and Applied Mathematics, 2013
Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters.
Proceedings of the ISWCS 2013, 2013
A comparison of computing architectures and parallelization frameworks based on a two-dimensional FDTD.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Open the Gates: Using High-level Synthesis towards programmable LDPC decoders on FPGAs.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013
High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Corrections to "MRC-Based RNS Reverse Converters for the Four-Moduli Sets 2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>2n+1</sup>-1 and 2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>2n</sup>, 2<sup>2n+1</sup>-1".
IEEE Trans. Circuits Syst. II Express Briefs, 2012
MRC-Based RNS Reverse Converters for the Four-Moduli Sets 2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>2n+1</sup>-1 and 2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>2n</sup>, 2<sup>2n+1</sup>-1.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Signal Process. Mag., 2012
Parallel Comput., 2012
Computation of Induced Dipoles in Molecular Mechanics Simulations Using Graphics Processors.
J. Chem. Inf. Model., 2012
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design.
EURASIP J. Wirel. Commun. Netw., 2012
Comput. J., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
Hierarchical Partitioning Algorithm for Scientific Computing on Highly Heterogeneous CPU + GPU Clusters.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Modeling and Evaluating Non-shared Memory CELL/BE Type Multi-core Architectures for Local Image and Video Processing.
J. Signal Process. Syst., 2011
IEEE Trans. Parallel Distributed Syst., 2011
A flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecs.
IEEE Trans. Consumer Electron., 2011
A tutorial overview on the properties of the discrete cosine transform for encoded image and video processing.
Signal Process., 2011
Int. J. Netw. Comput., 2011
High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
A new approach to system identification and parameter tuning with multiple model adaptive estimators.
Proceedings of the 7th International Symposium on Image and Signal Processing and Analysis, 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Measuring and Extraction of Biological Information on New Handheld Biochip-Based Microsystem.
IEEE Trans. Instrum. Meas., 2010
IEEE Trans. Instrum. Meas., 2010
Neurocomputing, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Unifying stream based and reconfigurable computing to design application accelerators.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the Real-Time Image and Video Processing 2010, 2010
p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems.
Proceedings of the Network and Operating System Support for Digital Audio and Video, 2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
An improved RNS reverse converter for the {2<sup>2n+1</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>-1} moduli set.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
High-Performance Computing on Heterogeneous Systems: Database Queries on CPU and GPU.
Proceedings of the High Performance Computing: From Grids and Clouds to Exascale, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010
2009
IEEE Trans. Instrum. Meas., 2009
Modelling and programming stream-based distributed computing based on the meta-pipeline approach.
Int. J. Parallel Emergent Distributed Syst., 2009
J. Comput. Sci. Technol., 2009
Neurocomputing, 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study.
Proceedings of the Embedded Computer Systems: Architectures, 2009
On the design of distributed autonomous embedded systems for biomedical applications.
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Fine-grain Parallelism Using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function.
Proceedings of the ICPP 2009, 2009
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
Proceedings of the High Performance Embedded Architectures and Compilers, 2009
Proceedings of the FCCM 2009, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Signal Process. Lett., 2008
Scalable Comput. Pract. Exp., 2008
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008
Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
A Parallel Algorithm for Advanced Video Motion Estimation on Multicore Architectures.
Proceedings of the Second International Conference on Complex, 2008
Proceedings of the 5th Conference on Computing Frontiers, 2008
Towards a Unified Model for the Retina - Static vs Dynamic Integrate and Fire Models.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008
2007
J. Real Time Image Process., 2007
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures.
IET Comput. Digit. Tech., 2007
EURASIP J. Embed. Syst., 2007
EURASIP J. Embed. Syst., 2007
EURASIP J. Adv. Signal Process., 2007
Developing and Integrating Lab Projects as Important Learning Components in an Embedded Systems Course.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the 6th International Symposium on Parallel and Distributed Computing (ISPDC 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
Proceedings of the International Conference on Image Processing, 2007
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Proceedings of the FPL 2007, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
Data buffering optimization methods toward a uniform programming interface for gpu-based applications.
Proceedings of the 4th Conference on Computing Frontiers, 2007
Design and implementation of a stream-based distributedcomputing platform using graphics processing units.
Proceedings of the 4th Conference on Computing Frontiers, 2007
Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007
2006
IEEE Trans. Parallel Distributed Syst., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer.
J. Interconnect. Networks, 2006
Proceedings of the Embedded Computer Systems: Architectures, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
IEEE Trans. Parallel Distributed Syst., 2005
Corrections to "A Universal Architecture for Designing Efficient Modulo 2<sup>n+1</sup> Multipliers".
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
On the Implementation and Evaluation of Berkeley Sockets on Maestro2 cluster computing environment.
Proceedings of the 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 2005
Least squares motion estimation algorithm in the compressed DCT domain for H.26x/MPEG-x video sequences.
Proceedings of the Advanced Video and Signal Based Surveillance, 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
J. Supercomput., 2004
List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures.
Parallel Comput., 2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 2004
Distributed Shared Memory System Based on the Maestro2 High Performance Cluster Network.
Proceedings of the 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 2004
On the performance of Maestro2 high performance network equipment, using new improvement techniques.
Proceedings of the 23rd IEEE International Performance Computing and Communications Conference, 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
2003
Automatic Synthesis of Motion Estimation Processors Based on a New Class of Hardware Architectures.
J. VLSI Signal Process., 2003
Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain.
Signal Process. Image Commun., 2003
An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
IEEE Trans. Circuits Syst. Video Technol., 2002
Proceedings of the 14th International Conference on Digital Signal Processing, 2002
Proceedings of the 14th International Conference on Digital Signal Processing, 2002
2001
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the 30th International Workshops on Parallel Processing (ICPP 2001 Workshops), 2001
Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001
Exploiting Unused Time Slots in List Scheduling Considering Communication Contention.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001
2000
Proceedings of the Vector and Parallel Processing, 2000
Proceedings of the Vector and Parallel Processing, 2000
In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000
1999
Proceedings of the Third IEEE Workshop on Multimedia Signal Processing, 1999
Applying Conditional Processing to Design Low-Power Array Processors for Motion Estimation.
Proceedings of the 1999 International Conference on Image Processing, 1999
On the Development of a Video CODEC for Low Bitrate Communication in General Purpose Computers.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1997
Proceedings of the Fourth International on High-Performance Computing, 1997