Kshitiz Tyagi

Orcid: 0000-0002-7310-0251

According to our database¹, Kshitiz Tyagi authored at least 3 papers between 2023 and 2026.

Collaborative distances:

Timeline

Book In proceedings Article PhD thesis Dataset Other

2026

Phase Noise Integration Limits for Jitter Estimation in Wireline Transmitters.

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2024

A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm<sup>2</sup>.

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Performance Bounds of ADC-Based Receivers Due to Clock Jitter.

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, May, 2023