Behzad Razavi

Orcid: 0000-0003-1168-9205

According to our database1, Behzad Razavi authored at least 164 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to high-speed communication circuits.".

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Performance Bounds of ADC-Based Receivers Due to Clock Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

A 56-GHz Fractional-N PLL With 110-fs Jitter.
IEEE J. Solid State Circuits, 2023

A 20-GHz PLL With 20.9-fs Random Jitter.
IEEE J. Solid State Circuits, 2023

A Study of Injection Locking in Oscillators and Frequency Dividers.
IEEE J. Solid State Circuits, 2023

A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation.
IEEE J. Solid State Circuits, 2023

A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
Relation Between INL and ACPR of RF DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 0.4-6 GHz Receiver for Cellular and WiFi Applications.
IEEE J. Solid State Circuits, 2022

A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance.
IEEE J. Solid State Circuits, 2022

A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022

A 56GHz 23mW Fractional-N PLL with 110fs Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 300GHz 52mW CMOS Receiver with On-Chip LO Generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Phase Noise Integration Limits for Jitter Calculation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Optimal Distribution of High-Speed Clocks on Transceiver Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Circuit Bandwidth Requirements for NRZ and PAM4 Signals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Jitter-Power Trade-Offs in PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 19-GHz PLL with 20.3-fs Jitter.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 27-73 GHz Injection-Locked Frequency Divider.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 0.4-6 GHz Receiver for LTE and WiFi.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Low-Power Techniques for Wireline Systems.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
A Digital RF Transmitter With Background Nonlinearity Correction.
IEEE J. Solid State Circuits, 2020

Lower Bounds on Power Consumption of Clock Generators for ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Instrument Design and Performance of the High-Frequency Airborne Microwave and Millimeter-Wave Radiometer.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019

An Inductorless 20-Gb/s CDR With High Jitter Tolerance.
IEEE J. Solid State Circuits, 2019

A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25f<sub>REF</sub>.
IEEE J. Solid State Circuits, 2018

An 80-Gb/s 44-mW Wireline PAM4 Transmitter.
IEEE J. Solid State Circuits, 2018

A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Alternative Analysis of Noise Folding in Fractional-N Synthesizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 32-mW 40-Gb/s CMOS NRZ transmitter.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Analysis of Second-Order Intermodulation in Miller Bandpass Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 40-Gb/s 14-mW CMOS Wireline Receiver.
IEEE J. Solid State Circuits, 2017

Introducing Our Sister Publication: IEEE Solid-State Circuits Letters.
IEEE J. Solid State Circuits, 2017

A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer.
IEEE J. Solid State Circuits, 2017

19.5 A 2.4GHz RF fractional-N synthesizer with 0.25fREF BW.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
On the Stability of Charge-Pump Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer.
IEEE J. Solid State Circuits, 2016

23.8 A 40Gb/s 14mW CMOS wireline receiver.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 25 Gb/s 5.8 mW CMOS Equalizer.
IEEE J. Solid State Circuits, 2015

An RF Receiver for Intra-Band Carrier Aggregation.
IEEE J. Solid State Circuits, 2015

A Low-Power CMOS Receiver for 5 GHz WLAN.
IEEE J. Solid State Circuits, 2015

A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply.
Proceedings of the Symposium on VLSI Circuits, 2015

A 40-Gb/s 9.2-mW CMOS equalizer.
Proceedings of the Symposium on VLSI Circuits, 2015

25.7 A 2.4GHz 4mW inductorless RF synthesizer.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

The future of radios.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
An 8 Bit 4 GS/s 120 mW CMOS ADC.
IEEE J. Solid State Circuits, 2014

Channel Selection at RF Using Miller Bandpass Filters.
IEEE J. Solid State Circuits, 2014

Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise.
IEEE J. Solid State Circuits, 2014

A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate.
IEEE J. Solid State Circuits, 2014

Analysis of Metastability in Pipelined ADCs.
IEEE J. Solid State Circuits, 2014

A 10-Bit 800-MHz 19-mW CMOS ADC.
IEEE J. Solid State Circuits, 2014

A receiver architecture for intra-band carrier aggregation.
Proceedings of the Symposium on VLSI Circuits, 2014

20.8 A 20mW GSM/WCDMA receiver with RF channel selection.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2.4 A 25Gb/s 5.8mW CMOS equalizer.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The role of translational circuits in RF receiver design.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Recent developments in RF receivers.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Analysis of Phase Noise in Phase/Frequency Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 10-b 1-GHz 33-mW CMOS ADC.
IEEE J. Solid State Circuits, 2013

Design Considerations for Interleaved ADCs.
IEEE J. Solid State Circuits, 2013

A Harmonic-Rejecting CMOS LNA for Broadband Radios.
IEEE J. Solid State Circuits, 2013

A 25-Gb/s 5-mW CMOS CDR/Deserializer.
IEEE J. Solid State Circuits, 2013

Charge steering: A low-power design paradigm.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 10-bit 1-GHz 33-mW CMOS ADC.
Proceedings of the Symposium on VLSI Circuits, 2012

A 25-Gb/s 5-mWCMOS CDR/deserializer.
Proceedings of the Symposium on VLSI Circuits, 2012

Problem of timing mismatch in interleaved ADCs.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2011

Transmitter Linearization by Beamforming.
IEEE J. Solid State Circuits, 2011

Low-Power CMOS Equalizer Design for 20-Gb/s Systems.
IEEE J. Solid State Circuits, 2011

Cellular and wireless LAN transceivers: From systems to circuit design.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Cognitive Radio Design Challenges and Techniques.
IEEE J. Solid State Circuits, 2010

A 20Gb/s 40mW equalizer in 90nm CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

CMOS phase-locked loops for frequency synthesis.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
The Role of PLLs in Future Wireline Transmitters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Design of Millimeter-Wave CMOS Radios: A Tutorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 10-Bit 500-MS/s 55-mW CMOS ADC.
IEEE J. Solid State Circuits, 2009

A 12-Bit 200-MHz CMOS ADC.
IEEE J. Solid State Circuits, 2009

A New Transceiver Architecture for the 60-GHz Band.
IEEE J. Solid State Circuits, 2009

Systematic Transistor and Inductor Modeling for Millimeter-Wave Design.
IEEE J. Solid State Circuits, 2009

U-PAS: A user-friendly ADC simulator for courses on analog design.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

A 10b 500MHz 55mW CMOS ADC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Challenges in the design of cognitive radios<sup>1</sup>.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A Millimeter-Wave Circuit Technique.
IEEE J. Solid State Circuits, 2008

A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider.
IEEE J. Solid State Circuits, 2008

A 60GHz CMOS Receiver Using a 30GHz LO.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Phase-locking in wireline systems: Present and future.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Heterodyne Phase Locking: A Technique for High-Speed Frequency Division.
IEEE J. Solid State Circuits, 2007

A Receiver Architecture for Dual-Antenna Systems.
IEEE J. Solid State Circuits, 2007

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers.
IEEE J. Solid State Circuits, 2007

Heterodyne Phase Locking: A Technique for High-Frequency Division.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

CMOS Transceivers at 60 GHz and Beyond1.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Considerations for Future RF Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A 60-GHz CMOS receiver front-end.
IEEE J. Solid State Circuits, 2006

A Fully Integrated UWB PHY in 0.13µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Frequency-Based Measurement of Mismatches Between Small Capacitors.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Mutual Injection Pulling Between Oscillators.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005

A UWB CMOS transceiver.
IEEE J. Solid State Circuits, 2005

Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology".
IEEE J. Solid State Circuits, 2005

Will continued process-node shrinks kill high-performance analog design?
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Multiband UWB transceivers.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A new receiver architecture for multiple-antenna systems.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A comparison of electrical and optical clock networks in nanometer technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A study of injection locking and pulling in oscillators.
IEEE J. Solid State Circuits, 2004

A 40-GHz frequency divider in 0.18-μm CMOS technology.
IEEE J. Solid State Circuits, 2004

Analysis and modeling of bang-bang clock and data recovery circuits.
IEEE J. Solid State Circuits, 2004

40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology.
IEEE J. Solid State Circuits, 2004

A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A low-power 2.4-GHz transmitter/receiver CMOS IC.
IEEE J. Solid State Circuits, 2003

A 5-GHz direct-conversion CMOS transceiver.
IEEE J. Solid State Circuits, 2003

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector.
IEEE J. Solid State Circuits, 2003

A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology.
IEEE J. Solid State Circuits, 2003

A stabilization technique for phase-locked frequency synthesizers.
IEEE J. Solid State Circuits, 2003

Broadband ESD protection circuits in CMOS technology.
IEEE J. Solid State Circuits, 2003

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology.
IEEE J. Solid State Circuits, 2003

A 2-GHz CMOS image-reject receiver with LMS calibration.
IEEE J. Solid State Circuits, 2003

RF CMOS transceivers for cellular telephony.
IEEE Commun. Mag., 2003

A study of injection pulling and locking in oscillators.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

Modeling of jitter in bang-bang clock and data recovery circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Prospects of CMOS technology for high-speed optical communication circuits.
IEEE J. Solid State Circuits, 2002

Challenges in the design of high-speed clock and data recovery circuits.
IEEE Commun. Mag., 2002

A noninvasive channel-select filter for a CMOS Bluetooth receiver.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

The role of monolithic transmission lines in high-speed integrated circuits.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
Stacked inductors and transformers in CMOS technology.
IEEE J. Solid State Circuits, 2001

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector.
IEEE J. Solid State Circuits, 2001

A 5.2-GHz CMOS receiver with 62-dB image rejection.
IEEE J. Solid State Circuits, 2001

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire.
IEEE J. Solid State Circuits, 2001

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data.
IEEE J. Solid State Circuits, 2001

Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems.
Proceedings of the 38th Design Automation Conference, 2001

Design of high-speed circuits for optical communication systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
An 8-bit 150-MHz CMOS A/D converter.
IEEE J. Solid State Circuits, 2000

A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology.
IEEE J. Solid State Circuits, 2000

Stacked inductors and 1-to-2 transformers in CMOS technology.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs.
IEEE J. Solid State Circuits, 1999

A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications.
IEEE J. Solid State Circuits, 1999

CMOS technology characterization for analog and RF design.
IEEE J. Solid State Circuits, 1999

RF transmitter architectures and circuits.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
A 900-MHz/1.8-GHz CMOS receiver for dual-band applications.
IEEE J. Solid State Circuits, 1998

RF IC Design Challenges.
Proceedings of the 35th Conference on Design Automation, 1998

Architectures and circuits for RF CMOS receivers.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

Oscillator jitter due to supply and substrate noise.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
A 2-GHz 1.6-mW phase-locked loop.
IEEE J. Solid State Circuits, 1997

Recent advances in RF integrated circuits.
IEEE Commun. Mag., 1997

Next-Generation RF Circuits and Systems.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
A 2.5-Gb/s 15-mW clock recovery circuit.
IEEE J. Solid State Circuits, 1996

A study of phase noise in CMOS oscillators.
IEEE J. Solid State Circuits, 1996

1995
A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply.
IEEE J. Solid State Circuits, December, 1995

A 2-GHz, 6-mW BiCMOS frequency synthesizer.
IEEE J. Solid State Circuits, December, 1995

Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology.
IEEE J. Solid State Circuits, July, 1995

Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS.
IEEE J. Solid State Circuits, February, 1995

1994
A 6 GHz 68 mW BiCMOS phase-locked loop.
IEEE J. Solid State Circuits, December, 1994

Design techniques for low-voltage high-speed digital bipolar circuits.
IEEE J. Solid State Circuits, March, 1994


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