Kumaravel Sundaram
Orcid: 0000-0003-2171-9420Affiliations:
- Vellore Institute of Techonology, School of Electronics Engineering, India
According to our database1,
Kumaravel Sundaram
authored at least 10 papers
between 2016 and 2024.
Collaborative distances:
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Bibliography
2024
Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
Blind Zone-Less Phase Frequency Detector for a Low-Power Phase-Locked Loop Architecture.
Circuits Syst. Signal Process., November, 2023
2021
An error efficient and low complexity approximate multi-bit adder for image processing applications.
Int. J. Circuit Theory Appl., 2021
A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology.
IET Circuits Devices Syst., 2021
2020
Int. J. Circuit Theory Appl., 2020
Power-efficient implementation of pseudo-random number generator using quantum dot cellular automata-based D Flip Flop.
Comput. Electr. Eng., 2020
2019
Modified recycling folded cascode OTA with enhancement in transconductanceand output impedance.
Turkish J. Electr. Eng. Comput. Sci., 2019
2018
A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
2016
A high linearity and high gain Folded Cascode LNA for narrowband receiver applications.
Microelectron. J., 2016