Kunitoshi Aono

According to our database, Kunitoshi Aono authored at least 10 papers between 1988 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput.

Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono

IEEE J. Solid State Circuits, 2013

Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM.

Akifumi Kawahara, Ken Kawai, Yuuichirou Ikeda, Yoshikazu Katoh, Ryotaro Azuma, Yuhei Yoshimoto, Kouhei Tanabe, Zhiqiang Wei, Takeki Ninomiya, Koji Katayama, Ryutaro Yasuhara, Shunsaku Muraoka, Atsushi Himeno, Naoki Yoshikawa, Hideaki Murase, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput.

Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Kouhei Tanabe, Toshihiro Nakamura, Yoshihiko Sumimoto, Naoki Yamada, Nobuyuki Nakai, Shoji Sakamoto, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Ken-ichi Origasa, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

1997

A DSP for DCT-based and wavelet-based video codecs for consumer applications.

Kiyoshi Okamoto, Takuya Jinbo, Toshiyuki Araki, Yasuo Iizuka, Hiromasa Nakajima, Minoru Takahata, Hisashi Inoue, Shun-ichi Kurohmaru, Tomonori Yonezawa, Kunitoshi Aono

IEEE J. Solid State Circuits, 1997

1994

A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC.

Masaki Toyokura, Hisashi Kodama, Eiji Miyagoshi, Koyoshi Okamoto, Masahiro Gion, Takayuki Minemaru, Akihiko Ohtani, Toshiyuki Araki, Hiroshi Takeno, Toshihide Akiyama, Brent Wilson, Kunitoshi Aono

IEEE J. Solid State Circuits, December, 1994

Video DSP architecture for MPEG2 codec.

Toshiyuki Araki, Masaki Toyokura, Toshihide Akiyama, Hiroshi Takeno, Brent Wilson, Kunitoshi Aono

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

1992

A video digital signal processor with a vector-pipeline architecture.

Kunitoshi Aono, Masaki Toyokura, Toshiyuki Araki, Akihiko Ohtani, Hisashi Kodama, Kiyoshi Okamoto

IEEE J. Solid State Circuits, December, 1992

The architecture of a vector digital signal processor for video coding.

Toshiyuki Araki, Masaki Toyokura, Masahiro Wakamori, Kunitoshi Aono

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

1990

An image signal multiprocessor on a single chip.

Masakatsu Maruyama, Hiroyuki Nakahira, Toshiyuki Araki, Shiro Sakiyama, Yoshitaka Kitao, Kunitoshi Aono, Haruyasu Yamada

IEEE J. Solid State Circuits, December, 1990

1988

A microprogrammable real-time image processor.

Haruyasu Yamada, Ken'ichi Hasegawa, Toshiki Mori, Hiroyuki Sakai, Kunitoshi Aono

IEEE J. Solid State Circuits, February, 1988