Kwang Sub Yoon

According to our database, Kwang Sub Yoon authored at least 14 papers between 1995 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A CMOS third order ΔΣ modulator with inverter-based integrators.

Jeong H. Choi, Kwang Sub Yoon

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016

A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier.

Seong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A CMOS buck converter with PFM / hysteretic mode.

Tae-Heon Lee, Jong-Gu Kim, Kwang Sub Yoon

Proceedings of the International SoC Design Conference, 2016

A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs.

Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, Kwang Sub Yoon

Proceedings of the International SoC Design Conference, 2016

2015

A CMOS hysteretic DC-DC buck converter with a low output ripple voltage.

Tae-Jin Chung, Kwang Sub Yoon

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

Design of a low power CMOS 10bit flash-SAR ADC.

Gi-Yoon Lee, Kwang Sub Yoon

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013

A CMOS high dimming ratio power-LED driver with a preloading inductor current method.

Kwang Sub Yoon, Keon Lee

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Design of high dimming ratio power-LED driver with preloading inductor current methodology.

Keon Lee, Dong-hun Lee, Su-hun Yang, Ji-hyun Park, Kwang Sub Yoon

Proceedings of the International SoC Design Conference, 2012

2011

Design of a 12-b asynchronous SAR CMOS ADC.

Jinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee

Proceedings of the International SoC Design Conference, 2011

2004

Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.

Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

A dual band CMOS VCO with a balanced duty cycle buffer.

Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

1999

A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range.

Hyuk-Jun Sung, Kwang Sub Yoon

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1996

A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load.

Jai-Sop Hyun, Kwang Sub Yoon

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

A Precision Output Conductance Model for Analog CMOS Circuit Simulations.

Jong Kug Seon, Kwang Sub Yoon

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995