Kyungmin Bae

Orcid: 0000-0002-6430-5175

According to our database1, Kyungmin Bae authored at least 46 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A rewriting-logic-with-SMT-based formal analysis and parameter synthesis framework for parametric time Petri nets.
CoRR, 2024

Formal Specification of Trusted Execution Environment APIs.
Proceedings of the Fundamental Approaches to Software Engineering, 2024

2023
Bounded STL Model Checking for Hybrid Systems (Invited Talk).
Proceedings of the 9th ACM SIGPLAN International Workshop on Formal Techniques for Safety-Critical Systems, 2023

Formal Model Engineering of Distributed CPSs Using AADL: From Behavioral AADL Models to Multirate Hybrid Synchronous AADL.
Proceedings of the Formal Aspects of Component Software - 19th International Conference, 2023

Symbolic Analysis and Parameter Synthesis for Time Petri Nets Using Maude and SMT Solving.
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2023

2022
Modeling and formal analysis of virtually synchronous cyber-physical systems in AADL.
Int. J. Softw. Tools Technol. Transf., 2022

An Extension of HybridSynchAADL and Its Application to Collaborating Autonomous UAVs.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Adaptation and Learning, 2022

Bounded Model Checking of PLC ST Programs using Rewriting Modulo SMT.
Proceedings of the 8th ACM SIGPLAN International Workshop on Formal Techniques for Safety-Critical Systems, 2022

Symbolic Reachability Analysis of Distributed Systems using Narrowing and Heuristic Search.
Proceedings of the 8th ACM SIGPLAN International Workshop on Formal Techniques for Safety-Critical Systems, 2022

Rewriting Logic Semantics and Symbolic Analysis for Parametric Timed Automata.
Proceedings of the 8th ACM SIGPLAN International Workshop on Formal Techniques for Safety-Critical Systems, 2022

STLmc: Robust STL Model Checking of Hybrid Systems Using SMT.
Proceedings of the Computer Aided Verification - 34th International Conference, 2022

2021
MSYNC: A Generalized Formal Design Pattern for Virtually Synchronous Multirate Cyber-physical Systems.
ACM Trans. Embed. Comput. Syst., 2021

Efficient SMT-Based Model Checking for Signal Temporal Logic.
Proceedings of the 36th IEEE/ACM International Conference on Automated Software Engineering, 2021

HybridSynchAADL: Modeling and Formal Analysis of Virtually Synchronous CPSs in AADL.
Proceedings of the Computer Aided Verification - 33rd International Conference, 2021

Composition of Languages, Models, and Analyses.
Proceedings of the Composing Model-Based Analysis Tools, 2021


2020
Formal aspects of component software (FACS 2018).
Sci. Comput. Program., 2020

2019
Symbolic state space reduction with guarded terms for rewriting modulo SMT.
Sci. Comput. Program., 2019

Bounded model checking of signal temporal logic properties using syntactic separation.
Proc. ACM Program. Lang., 2019

2017
Modular SMT-based analysis of nonlinear hybrid systems.
Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Guarded Terms for Rewriting Modulo SMT.
Proceedings of the Formal Aspects of Component Software - 14th International Conference, 2017

2016
A Term Rewriting Approach to Analyze High Level Petri Nets.
Proceedings of the 10th International Symposium on Theoretical Aspects of Software Engineering, 2016

A Hybrid Architecture for Correct-by-Construction Hybrid Planning and Control.
Proceedings of the NASA Formal Methods - 8th International Symposium, 2016

SMT-Based Analysis of Virtually Synchronous Distributed Hybrid Systems.
Proceedings of the 19th International Conference on Hybrid Systems: Computation and Control, 2016

An Architecture for Hybrid Planning and Execution.
Proceedings of the Planning for Hybrid Systems, 2016

2015
Model checking linear temporal logic of rewriting formulas under localized fairness.
Sci. Comput. Program., 2015

Designing and verifying distributed cyber-physical systems using Multirate PALS: An airplane turning control system case study.
Sci. Comput. Program., 2015

SMT Encoding of Hybrid Systems in dReal.
Proceedings of the 1st and 2nd International Workshop on Applied veRification for Continuous and Hybrid Systems, 2015

Hybrid Multirate PALS.
Proceedings of the Logic, Rewriting, and Concurrency, 2015

2014
Rewriting-based model checking methods
PhD thesis, 2014

Formal patterns for multirate distributed real-time systems.
Sci. Comput. Program., 2014

Infinite-State Model Checking of LTLR Formulas Using Narrowing.
Proceedings of the Rewriting Logic and Its Applications - 10th International Workshop, 2014

Predicate Abstraction of Rewrite Theories.
Proceedings of the Rewriting and Typed Lambda Calculi - Joint International Conference, 2014

Definition, Semantics, and Analysis of Multirate Synchronous AADL.
Proceedings of the FM 2014: Formal Methods, 2014

2013
Abstract Logical Model Checking of Infinite-State Systems Using Narrowing.
Proceedings of the 24th International Conference on Rewriting Techniques and Applications, 2013

2012
Verifying hierarchical Ptolemy II discrete-event models using Real-Time Maude.
Sci. Comput. Program., 2012

PALS-Based Analysis of an Airplane Multirate Control System in Real-Time Maude
Proceedings of the Proceedings First International Workshop on Formal Techniques for Safety-Critical Systems, 2012

Model Checking LTLR Formulas under Localized Fairness.
Proceedings of the Rewriting Logic and Its Applications - 9th International Workshop, 2012

The SynchAADL2Maude Tool.
Proceedings of the Fundamental Approaches to Software Engineering, 2012

Formal Patterns for Multi-rate Distributed Real-Time Systems.
Proceedings of the Formal Aspects of Component Software, 9th International Symposium, 2012

2011
Synchronous AADL and Its Formal Analysis in Real-Time Maude.
Proceedings of the Formal Methods and Software Engineering, 2011

State/Event-Based LTL Model Checking under Parametric Generalized Fairness.
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2010
Extending the Real-Time Maude Semantics of Ptolemy to Hierarchical DE Models
Proceedings of the Proceedings First International Workshop on Rewriting Techniques for Real-Time Systems, 2010

The Linear Temporal Logic of Rewriting Maude Model Checker.
Proceedings of the Rewriting Logic and Its Applications - 8th International Workshop, 2010

2009
Verifying Ptolemy II Discrete-Event Models Using Real-Time Maude.
Proceedings of the Formal Methods and Software Engineering, 2009

2008
A Rewriting-Based Model Checker for the Linear Temporal Logic of Rewriting.
Proceedings of the Ninth International Workshop on Rule-Based Programming, 2008


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