Laure Abdallah

According to our database1, Laure Abdallah authored at least 6 papers between 2015 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2018
Reducing AFDX jitter in a mixed NoC/AFDX architecture.
Proceedings of the 14th IEEE International Workshop on Factory Communication Systems, 2018

2017
Worst-case delay analysis of core-to-IO flows over many-cores architectures. (Analyse des délais pire cas des flux entre coeur et interfaces entrées/sorties sur des architectures pluri-coeurs).
PhD thesis, 2017

Towards a mixed NoC/AFDX architecture for avionics applications.
Proceedings of the IEEE 13th International Workshop on Factory Communication Systems, 2017

2016
Poster Abstract: I/O Contention Aware Mapping of Multi-Criticalities Real-Time Applications over Many-Core Architectures.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

2015
Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015


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