Li-Hsun Chen

According to our database1, Li-Hsun Chen authored at least 10 papers between 2000 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2007
Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs.
IEEE Trans. Circuits Syst. Video Technol., 2007

A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding.
EURASIP J. Adv. Signal Process., 2007

2006
A Low-Power Folded Programmable FIR Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A hardware-efficient FIR architecture with input-data and tap folding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A high-efficiency reconfigurable digital signal processor for multimedia computing.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A reconfigurable digital signal processor architecture for high-efficiency MPEG-4 video encoding.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

2001
A low-complexity and high-speed Booth-algorithm FIR architecture.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Determination of radix numbers of the Booth algorithm for the optimized programmable FIR architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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