Lin Wang

According to our database, Lin Wang authored at least 5 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.

Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation.

Lin Wang, Yong Chen, Chaowei Yang, Xionghui Zhou, Mei Han, Paolo Stefano Crovetti, Pui-In Mak, Rui Paulo Martins

Int. J. Circuit Theory Appl., May, 2023

2022

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.

Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins

IEEE J. Solid State Circuits, 2022

A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector.

Xinyi Ge, Yong Chen, Lin Wang, Nan Qi, Pui-In Mak, Rui Paulo Martins

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.

Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022