Xiaoteng Zhao

According to our database, Xiaoteng Zhao authored at least 13 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs_rms Integrated Jitter and -250.8-dB FOM_PLL.

Depeng Sun, Linguo Huang, Rong Zhou, Feng Bu, Lisheng Chen, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Zhangming Zhu

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A wideband low power RF Receiver Front-End for Internet-of-Things applications.

Rong Zhou, Jianhang Yang, Linwei Wang, Xiaoteng Zhao, Shubin Liu, Depeng Sun

Microelectron. J., February, 2024

A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications.

Rong Zhou, Linwei Wang, Jianhang Yang, Zhen Li, Xiaoteng Zhao, Shubin Liu

Microelectron. J., February, 2024

2023

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.

Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A 0.012mm² 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply.

Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.

Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins

IEEE J. Solid State Circuits, 2022

A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS.

Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins

IEEE J. Solid State Circuits, 2022

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.

Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS.

Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A 0.0285mm² 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS.

Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter.

Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Very Large Scale Integr. Syst., 2019

A 0.0018-mm² 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-g_m Cell.

Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS.

Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019