Lingxin Meng

According to our database, Lingxin Meng authored at least 14 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 93.6-dB SNDR Fully Dynamic CT-DT Noise-Shaping SAR ADC With Closed-Loop Capacitively Coupled Two-Stage FIA.

Lingxin Meng, Shuang Song, Menglian Zhao, Zhichao Tan

IEEE J. Solid State Circuits, June, 2025

An 871 nW 96.2 dB SNDR Pipelined Second-Order Noise-Shaping SAR ADC Employing Charge-Efficient CLS-Assisted Residue Amplifier.

Shan Zhang, Lingxin Meng, Zhaonan Lu, Shuang Song, Wanyuan Qu, Menglian Zhao, Zhichao Tan

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025

SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection.

Lingxin Meng, Menglian Zhao, Zhichao Tan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 1V 9-86 fJ/Conv.Step 72.5dB-SNDR Level-Crossing Pipelined ADC with Triggered Sampling and Level Feedback.

Zexin Wang, Lingxin Meng, Menglian Zhao, Mengyu Li, Shuang Song, Zhichao Tan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

A Partially Feedback NSSAR Embedded Third-Order Delta-Sigma Modulator With Gain-Boosted Two-Stage FIAs.

Lingxin Meng, Junsheng Chen, Menglian Zhao, Zhichao Tan

IEEE J. Solid State Circuits, September, 2024

A 0.5V 723nW 84.3dB-SNDR Dynamic Zoom ADC with CLS-Assisted Capacitively-Biased FIA.

Weiqiang Chen, Lingxin Meng, Yining Zhao, Menglian Zhao, Zhichao Tan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIA.

Shan Zhang, Lingxin Meng, Zhaonan Lu, Wanyuan Qu, Shuang Song, Menglian Zhao, Zhichao Tan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 93.6dB-SNDR 5kHz-BW Fully Dynamic Hybrid CT-DT Noise Shaping SAR ADC.

Lingxin Meng, Menglian Zhao, Zhichao Tan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC.

Lingxin Meng, Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan

IEEE J. Solid State Circuits, 2023

A 94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC Using OTA-FIA Based Integrators.

Xirui Hao, Junsheng Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Low-Frequency Features Optimization for Transferability Enhancement in Radar Target Adversarial Attack.

Bo Peng, Bowen Peng, Jie Zhou, Xichen Huang, Lingxin Meng, Xunzhang Gao

Proceedings of the Artificial Neural Networks and Machine Learning, 2023

An 18.2μW 101.1dB DR Fully-Dynamic ΔΣ ADC with Partially-Feedback Noise-Shaping Quantizer and CLS-Embedded Two-Stage FIAs.

Lingxin Meng, Junsheng Chen, Menglian Zhao, Zhichao Tan

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image Sensors.

Junsheng Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2018

Inverse optimal design of input-to-state stabilisation for affine nonlinear systems with input delays.

Xiushan Cai, Lingxin Meng, Wei Zhang, Leipo Liu

Int. J. Syst. Sci., 2018