Le Ye
Orcid: 0000-0003-0599-7762
According to our database1,
Le Ye
authored at least 66 papers
between 2009 and 2024.
Collaborative distances:
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Bibliography
2024
A 0.39-mm<sup>2</sup> Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC.
IEEE J. Solid State Circuits, February, 2024
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Sci. China Inf. Sci., October, 2023
IEEE J. Solid State Circuits, September, 2023
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
IEEE J. Solid State Circuits, 2023
IEEE J. Solid State Circuits, 2023
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Microelectron. J., 2022
A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/differential configurable input modes.
Microelectron. J., 2022
A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers.
IEEE J. Solid State Circuits, 2022
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
IEEE J. Solid State Circuits, 2021
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network.
IEEE J. Solid State Circuits, 2021
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.
IEEE J. Solid State Circuits, 2021
12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
5.1 A 1.5μW 0.135pJ·%RH<sup>2</sup> CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst., 2020
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEICE Electron. Express, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2015
Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Sci. China Inf. Sci., 2013
SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Widely reconfigurable 8<sup>th</sup>-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A 0.47mW 6<sup>th</sup>-order 20MHz active filter using highly power-efficient Opamp.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
-99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
IEEE J. Solid State Circuits, 2010
A 17-tap 3.5 Gbps finite impulse response pulse shaping filter for 60 GHz transmitter with QPSK modulation.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009