Longyu Ma

Orcid: 0000-0002-3350-004X

According to our database1, Longyu Ma authored at least 20 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Novel Computing Paradigm for MobileNetV3 using Memristor.
CoRR, 2024

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges.
CoRR, 2024

Edge AI Empowered Physical Layer Security for 6G NTN: Potential Threats and Future Opportunities.
CoRR, 2024

Joint Source-Channel Coding System for 6G Communication: Design, Prototype and Future Directions.
IEEE Access, 2024

2023
Joint Source-Channel Coding System for 6G Communication: Design, Prototype and Future Directions.
CoRR, 2023

A Topology Control Algorithm based on Theil's Entropy lmproved Potential Game for Wireless Sensor Networks.
Proceedings of the 8th International Conference on Cyber Security and Information Engineering, 2023

2022
Implementation for JSCC Scheme Based on QC-LDPC Codes.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021
An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes.
CoRR, 2021

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes.
IEEE Access, 2021

A New Method for Bearing Steel Ball Surface Detection with Eddy Current Sensor.
Proceedings of the Intelligent Robotics and Applications - 14th International Conference, 2021

A Highly Integrated RISC-V Based SoC for On-Board Unit in ETC System.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

A Dynamically Reconfigurable QC-LDPC Implementation for Iris Recognition.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

CNN Accelerator with Non-Blocking Network Design.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2020
A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Iris Recognition System Implementation Improved by QC-LDPC codes.
Proceedings of the 2nd IEEE Global Conference on Life Sciences and Technologies, 2020

An Iris Recognition System Implementation with Error Correction Capability by Reusing WiFi Standard LDPC Codes.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

A RISC-V SoC for Mobile Payment Based on Visible Light Communication.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes.
Proceedings of the International Conference on Field-Programmable Technology, 2019

A Novel Data Packing Technique for QC-LDPC Decoder Architecture applied to NAND flash controller.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019


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