Chiu-Wing Sham

Orcid: 0000-0001-7007-6746

According to our database1, Chiu-Wing Sham authored at least 82 papers between 2001 and 2024.

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Bibliography

2024
JPEG-compatible Joint Image Compression and Encryption Algorithm with File Size Preservation.
ACM Trans. Multim. Comput. Commun. Appl., April, 2024

Batch medical image encryption using 3D Latin cube-based simultaneous permutation and diffusion.
Signal Image Video Process., April, 2024

Attention-based deep supervised hashing for near duplicate video retrieval.
Neural Comput. Appl., April, 2024

An efficient chaotic image encryption scheme using simultaneous permutation-diffusion operation.
Vis. Comput., March, 2024

A fast selective encryption scheme for H.264/AVC video with syntax-preserving and zero bit rate expansion.
Signal Image Video Process., February, 2024

A Novel Computing Paradigm for MobileNetV3 using Memristor.
CoRR, 2024

Joint Source-Channel Coding System for 6G Communication: Design, Prototype and Future Directions.
IEEE Access, 2024

2023
A one-time-pad-like chaotic image encryption scheme using data steganography.
J. Inf. Secur. Appl., November, 2023

Automatic skin lesion classification using a novel densely connected convolutional network integrated with an attention module.
J. Ambient Intell. Humaniz. Comput., July, 2023

Adversarial co-training for semantic segmentation over medical images.
Comput. Biol. Medicine, May, 2023

Novel CNN Accelerator Design With Dual Benes Network Architecture.
IEEE Access, 2023

A RISC-V Based SoC with Configurable CPK Sensor Interface for ECU on Motorcycle.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022
Spatially Coupled PLDPC-Hadamard Convolutional Codes.
IEEE Trans. Commun., 2022

Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A fast parallel batch image encryption algorithm using intrinsic properties of chaos.
Signal Process. Image Commun., 2022

Protection of image ROI using chaos-based encryption and DCNN-based object detection.
Neural Comput. Appl., 2022

A more compact object detector head network with feature enhancement and relational reasoning.
Neurocomputing, 2022

CODH++: Macro-semantic differences oriented instance segmentation network.
Expert Syst. Appl., 2022

Uncertainty-aware deep co-training for semi-supervised medical image segmentation.
Comput. Biol. Medicine, 2022

HSNet: A hybrid semantic network for polyp segmentation.
Comput. Biol. Medicine, 2022

Uncertainty teacher with dense focal loss for semi-supervised medical image segmentation.
Comput. Biol. Medicine, 2022

Implementation for JSCC Scheme Based on QC-LDPC Codes.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021
Protograph-Based LDPC Hadamard Codes.
IEEE Trans. Commun., 2021

Layered Decoding for Protograph-Based Low-Density Parity-Check Hadamard Codes.
IEEE Commun. Lett., 2021

Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes.
CoRR, 2021

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes.
CoRR, 2021

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes.
IEEE Access, 2021

A Highly Integrated RISC-V Based SoC for On-Board Unit in ETC System.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

A Dynamically Reconfigurable QC-LDPC Implementation for Iris Recognition.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

CNN Accelerator with Non-Blocking Network Design.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2020
A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An Ultimate-Shannon-Limit-Approaching Gbps Throughput Encoder/Decoder System.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Protograph-Based Low-Density Parity-Check Hadamard Codes.
CoRR, 2020

Hardware Design of Concatenated Zigzag Hadamard Encoder/Decoder System With High Throughput.
IEEE Access, 2020

Energy Efficient Fixed-point Inference System of Convolutional Neural Network.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Iris Recognition System Implementation Improved by QC-LDPC codes.
Proceedings of the 2nd IEEE Global Conference on Life Sciences and Technologies, 2020

Preliminary study of applied binary neural networks for neural cryptography.
Proceedings of the GECCO '20: Genetic and Evolutionary Computation Conference, 2020

An Iris Recognition System Implementation with Error Correction Capability by Reusing WiFi Standard LDPC Codes.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020

A RISC-V SoC for Mobile Payment Based on Visible Light Communication.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
Joint Shuffled Scheduling Decoding Algorithm for DP-LDPC Codes-Based JSCC Systems.
IEEE Wirel. Commun. Lett., 2019

An SoC for Qi-compliant Wireless Power Transmitter With Enhanced EMI Performance.
Proceedings of the 6th International Conference on Systems and Informatics, 2019

Evolved Binary Neural Networks Through Harnessing FPGA Capabilities.
Proceedings of the International Conference on Field-Programmable Technology, 2019

SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes.
Proceedings of the International Conference on Field-Programmable Technology, 2019

A Visible Light Communication Based Integrated Circuit for Mobile Payment.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

A Novel Data Packing Technique for QC-LDPC Decoder Architecture applied to NAND flash controller.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Using Neuroevolved Binary Neural Networks to solve reinforcement learning environments.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits.
ACM Trans. Design Autom. Electr. Syst., 2018

Tree-Permutation-Matrix Based LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Optimization Approach for an RLL-Constrained LDPC Coded Recording System Using Deliberate Flipping.
IEEE Commun. Lett., 2018

A Turbo-Hadamard Encoder/Decoder System with Hundreds of Mbps Throughput.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

2017
Unequal protection approach for RLL-constrained LDPC coded recording system using deliberate flipping.
Proceedings of the International SoC Design Conference, 2017

Design of a high-throughput low-latency extended golay decoder.
Proceedings of the 23rd Asia-Pacific Conference on Communications, 2017

Design and error performance of punctured hadamard codes.
Proceedings of the 23rd Asia-Pacific Conference on Communications, 2017

2016
A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

On using the cyclically-coupled QC-LDPC codes in future SSDs.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
SIAR: Customized real-time interactive router for analog circuits.
Integr., 2015

An architecture-algorithm co-design of artificial intelligence for Trax player.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

2014
Length matching in detailed routing for analog and mixed signal circuits.
Microelectron. J., 2014

Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach.
Integr., 2014

Slicing Floorplans with Handling Symmetry and General Placement Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A high throughput Gaussian noise generator.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Fast Power- and Slew-Aware Gated Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A new clock network synthesizer for modern VLSI designs.
Integr., 2012

A layered QC-LDPC decoder architecture for high speed communication system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Efficient Decoding of QC-LDPC Codes Using GPUs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

2010
Clock Network Synthesis with Concurrent Gate Insertion.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

A dual-MST approach for clock network synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Congestion prediction in early stages of physical design.
ACM Trans. Design Autom. Electr. Syst., 2009

Block flipping and white space distribution for wirelength minimization.
Integr., 2009

2008
Optimizing wirelength and routability by searching alternative packings in floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
Area reduction by deadspace utilization on interconnect optimized floorplan.
ACM Trans. Design Autom. Electr. Syst., 2007

2006
Optimal cell flipping in placement and floorplanning.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Congestion prediction in early stages.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Congestion prediction in floorplanning.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
Routability-driven floorplanner with buffer block planning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Interconnect-driven floorplanning by searching alternative packings.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Congestion Estimation with Buffer Planning in Floorplan Design.
Proceedings of the 2002 Design, 2002

2001
A bitstream reconfigurable FPGA implementation of the WSAT algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2001


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