Luca Ravezzi

Orcid: 0000-0003-2427-6311

According to our database1, Luca Ravezzi authored at least 9 papers between 2006 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Study of the Design Criteria for 4-Stage, Pseudo-Differential Ring Oscillators to Self-Start From Any Initial State.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026

2021
Failure in Ring Oscillators With Capacitive Load.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2018
Up-Conversion of Clock Phase Noise in Plesiochronous Data Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2015
Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC.
IEEE J. Solid State Circuits, 2015

2014
5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC.
Proceedings of the ESSCIRC 2014, 2014

2012
A 3-stage Pseudo Single-phase Flip-flop family.
Proceedings of the Symposium on VLSI Circuits, 2012

2009
Single-ended transceiver design techniques for 5.33Gb/s graphics applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
Data Recovery and Retiming for the Fully Buffered DIMM 4.8Gb/s Serial Links.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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