Luka Daoud

According to our database, Luka Daoud authored at least 18 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Efficient mitigation technique for Black Hole router attack in Network-on-Chip.

Luka Daoud, Nader Rafla

Microprocess. Microsystems, October, 2022

Energy-Efficient Black Hole Router Detection in Network-on-Chip.

Luka Daoud, Nader Rafla

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

2020

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA.

Fady Hussein, Luka Daoud, Nader Rafla

Microprocess. Microsystems, 2020

A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching.

Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla

Microprocess. Microsystems, 2020

2019

Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip.

Luka Daoud, Nader Rafla

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Detection and prevention protocol for black hole attack in network-on-chip.

Luka Daoud, Nader Rafla

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Analysis of Black Hole Router Attack in Network-on-Chip.

Luka Daoud, Nader Rafla

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS).

Luka Daoud, Fady Hussein, Nader Rafla

Proceedings of 34th International Conference on Computers and Their Applications, 2019

2018

Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol.

Muhammad Kamran Latif, H. S. Jacinto, Luka Daoud, Nader Rafla

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Routing Aware and Runtime Detection for Infected Network-on-Chip Routers.

Luka Daoud, Nader Rafla

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration.

Luka Daoud, Fady Hussein, Nader Rafla

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Secure Network-on-Chip Architectures for MPSoC: Overview and Challenges.

Luka Daoud

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only).

Fady Hussein, Luka Daoud, Nader Rafla

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only).

Luka Daoud, Muhammad Kamran Latif, Nader Rafla

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

High level synthesis using vivado HLS for optimizations of SHA-3.

H. S. Jacinto, Luka Daoud, Nader Rafla

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

Zynq-based SoC implementation of an induction machine control algorithm.

Danyal Mohammadi, Luka Daoud, Nader Rafla, Said Ahmed-Zaid

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2014

A Survey on Design and Implementation of Floating Point Adder in FPGA.

Luka Daoud, Dawid Zydek, Henry Selvaraj

Proceedings of the Progress in Systems Engineering, 2014

2013

A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing.

Luka Daoud, Dawid Zydek, Henry Selvaraj

Proceedings of the Advances in Systems Science, 2013