Henry Selvaraj

According to our database1, Henry Selvaraj authored at least 63 papers between 1995 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
FPGA Implementation for Epileptic Seizure Detection Using Amplitude and Frequency Analysis of EEG Signals.
Proceedings of the 25th International Conference on Systems Engineering, 2017

Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models.
Proceedings of the 25th International Conference on Systems Engineering, 2017

Improved Genetic Algorithm for Finite-Horizon Optimal Control of Nonlinear Systems.
Proceedings of the 25th International Conference on Systems Engineering, 2017

Interconnection Networks Efficiency in System-on-Chip Distributed Computing System: Concentrated Mesh and Fat Tree.
Proceedings of the 25th International Conference on Systems Engineering, 2017

2016
Energy-Efficient Computing Solutions for Internet of Things with ZigBee Reconfigurable Devices.
IJSI, 2016

2015
FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm.
International Journal of Computational Intelligence and Applications, 2015

Energy-efficient distributed computing solutions for Internet of Things with ZigBee devices.
Proceedings of the 14th IEEE/ACIS International Conference on Computer and Information Science, 2015

2014
A Survey on Design and Implementation of Floating Point Adder in FPGA.
Proceedings of the Progress in Systems Engineering, 2014

UAV Cooperative Data Processing Using Distributed Computing Platform.
Proceedings of the Progress in Systems Engineering, 2014

Distributed Processing Applications for UAV/drones: A Survey.
Proceedings of the Progress in Systems Engineering, 2014

2013
Fast FPGA-based fault injection tool for embedded processors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Matrix Multiplication in Multiphysics Systems Using CUDA.
Proceedings of the Advances in Systems Science, 2013

A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing.
Proceedings of the Advances in Systems Science, 2013

Tracker-Node Model for Energy Consumption in Reconfigurable Processing Systems.
Proceedings of the Advances in Systems Science, 2013

2012
Accelerating High Performance Computing Applications: Using CPUs, GPUs, Hybrid CPU/GPU, and FPGAs.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

Overlay-NoC and H-Phy based computing using modern Chip Multiprocessors.
Proceedings of the 2012 IEEE International Conference on Electro/Information Technology, 2012

2011
Supervised Classification of White Blood Cells by Fusion of Color Texture Features and Neural Network.
International Journal of Computational Intelligence and Applications, 2011

Fast and efficient processor allocation algorithm for torus-based chip multiprocessors.
Computers & Electrical Engineering, 2011

Energy characteristic of a processor allocator and a network-on-chip.
Applied Mathematics and Computer Science, 2011

Extended Analysis of Resource Assignment in Modern Chip Multiprocessors.
Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011

Ear-Slicing and Quality Triangulation.
Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011

2010
Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors.
Microprocessors and Microsystems - Embedded Hardware Design, 2010

Hybrid Approach for Brain Tumor Segmentation in Magnetic Resonance Images Using Cellular Neural Networks and Optimization Techniques.
International Journal of Computational Intelligence and Applications, 2010

Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors.
Proceedings of the Seventh International Conference on Information Technology: New Generations, 2010

2009
Editorial: Applications of Computational Intelligence.
International Journal of Computational Intelligence and Applications, 2009

Constrained Disjoint Paths in Geometric Networks.
International Journal of Computational Intelligence and Applications, 2009

Processor Allocation Problem for NoC-Based Chip Multiprocessors.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2008
Iteration-Free Fractal Coding for Image Compression Using Genetic Algorithm.
International Journal of Computational Intelligence and Applications, 2008

2007
An efficient variable partitioning approach for functional decomposition of circuits.
Journal of Systems Architecture, 2007

Placement-Directed Behavioral Synthesis Scheme for Simultaneous Scheduling Binding and Partitioning with Resources Operating at Multiple Voltages.
I. J. Comput. Appl., 2007

Scheduling and optimal voltage selection with multiple supply voltages under resource constraints.
Integration, 2007

Interference Aware Routing in Sensor Network.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

2006
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages.
The Journal of Supercomputing, 2006

Abnormality Detection in Brain MR Images Using Minimum Error Thresholding Method.
International Journal of Computational Intelligence and Applications, 2006

Support Vector Machine Based Automatic Classification of Human Brain Using MR Image Features.
International Journal of Computational Intelligence and Applications, 2006

Functional Decomposition - the Value and Implication for Both Neural Networks and Digital Designing.
International Journal of Computational Intelligence and Applications, 2006

Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition.
International Journal of Computational Intelligence and Applications, 2006

2005
Reconfigurable embedded systems: Synthesis, design and application.
Journal of Systems Architecture, 2005

An application of functional decomposition in ROM-based FSM implementation in FPGA devices.
Journal of Systems Architecture, 2005

Multiple voltage and frequency scheduling for power minimization.
Journal of Systems Architecture, 2005

Multiple voltage synthesis scheme for low power design under timing and resource constraints.
Integrated Computer-Aided Engineering, 2005

Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Synthesis Scheme for Low Power Designs with Multiple Supply Voltages by Heuristic Algorithms.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Synthesis scheme for low power designs with multiple supply voltages by tabu search.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Hybrid Approach to a Classification Problem.
Proceedings of the Intelligent Information Processing and Web Mining, 2004

Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints.
Proceedings of the International Conference on VLSI, 2003

A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002
Performance Driven Circuit Clustering and Partitioning.
Proceedings of the 2002 International Symposium on Information Technology (ITCC 2002), 2002

FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition.
Proceedings of the 2002 International Symposium on Information Technology (ITCC 2002), 2002

2001
Functional Decomposition and Its Applications in Machine Learning and Neural Networks.
International Journal of Computational Intelligence and Applications, 2001

A variable partition approach for disjoint decomposition.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis.
Proceedings of the Rough Sets and Current Trends in Computing, 2000

An Improved Column Compatibility Approach for Partition Based Functional Decomposition.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1998
Decomposition Strategies and their Performance in Fpga-Based Technology Mapping.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1995
A balanced multilevel decomposition method.
Proceedings of the 1995 European Design and Test Conference, 1995


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