M. C. Bhuvaneswari

According to our database, M. C. Bhuvaneswari authored at least 6 papers between 2009 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2013

Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits.

S. Jayanthy, M. C. Bhuvaneswari, M. Prabhu

Int. J. Comput. Appl. Technol., 2013

2012

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths.

D. S. Harish Ram, M. C. Bhuvaneswari, Shanthi S. Prabhu

VLSI Design, 2012

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.

S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha

VLSI Design, 2012

Task allocation in distributed computing systems using adaptive particle swarm optimisation.

G. Subashini, M. C. Bhuvaneswari

Int. J. Comput. Appl. Technol., 2012

2011

A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths.

D. S. Harish Ram, M. C. Bhuvaneswari, S. M. Logesh

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2009

Efficient multi-objective genetic algorithm for hardware-software partitioning in embedded system design: ENGA.

M. Jagadeeswari, M. C. Bhuvaneswari

Int. J. Comput. Appl. Technol., 2009