M. Jagadesh Kumar

According to our database, M. Jagadesh Kumar authored at least 3 papers between 2004 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications.

Vivek Asthana, M. Jagadesh Kumar, Ayush Kulshrestha, Munish Kumar, Saikat Kumar Banik, Shruti Aggarwal

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2006

Phase Change Memory Faults.

M. Jagadesh Kumar, Ali A. Orouji

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004

Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies.

Anurag Chaudhry, M. Jagadesh Kumar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004