Maitri Iyer
Orcid: 0009-0008-8889-3187
According to our database1,
Maitri Iyer authored at least 2 papers
between 2024 and 2025.
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Bibliography
2025
Bridging Cryptographic Robustness and Hardware Efficiency: A Comprehensive Analysis of S-Box Design Methodologies for SoC Integration.
Proceedings of the 18th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2025
2024
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024