Jai Gopal Pandey

Orcid: 0000-0001-9937-7438

According to our database1, Jai Gopal Pandey authored at least 25 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher.
J. Real Time Image Process., April, 2024

2023
Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends.
Comput. Secur., June, 2023

An RTL Implementation of the Data Encryption Standard (DES).
CoRR, 2023

PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations.
Proceedings of the Next Generation Arithmetic - 4th International Conference, 2023

2022
An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021
GIFT cipher usage in image data security: hardware implementations, performance and statistical analyses.
J. Real Time Image Process., 2021

An embedded FPGA-SoC framework and its usage in moving object tracking application.
Des. Autom. Embed. Syst., 2021

A Hardware Generator for Posit Arithmetic and its FPGA Prototyping.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020
A Highly Stable and Robust 7T SRAM Cell using Memristor.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications.
Microelectron. J., 2019

Hardware architectures for PRESENT block cipher and their FPGA implementations.
IET Circuits Devices Syst., 2019

A Novel Design of SRAM Using Memristors at 45 nm Technology.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An Ultra Low Power AES Architecture for IoT.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An RNS Implementation of the Elliptic Curve Cryptography for IoT Security.
Proceedings of the First IEEE International Conference on Trust, 2019

2018
A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2017
An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Architectures and algorithms for image and video processing using FPGA-based platform.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014


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