Major Bhadauria

According to our database1, Major Bhadauria authored at least 10 papers between 2007 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
An approach to resource-aware co-scheduling for CMPs.
Proceedings of the 24th International Conference on Supercomputing, 2010

Portable, scalable, per-core power estimation for intelligent resource management.
Proceedings of the International Green Computing Conference 2010, 2010

2009
Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.
Trans. HiPEAC, 2009

Real time power estimation and thread scheduling via performance counters.
SIGARCH Computer Architecture News, 2009

Understanding PARSEC performance on contemporary CMPs.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Prediction-based power estimation and scheduling for CMPs.
Proceedings of the 23rd international conference on Supercomputing, 2009

PARSEC: hardware profiling of emerging workloads for CMP design.
Proceedings of the 23rd international conference on Supercomputing, 2009

Accomodating Diversity in CMPs with Heterogeneous Frequencies.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2008
Optimizing thread throughput for multithreaded workloads on memory constrained CMPs.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007


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