Maneesha Gupta

Orcid: 0000-0003-2495-678X

According to our database1, Maneesha Gupta authored at least 44 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques.
J. Circuits Syst. Comput., February, 2024

2023
Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique.
Integr., May, 2023

Design of Fractional-Order Chebyshev Low-Pass Filter for Optimized Magnitude Response Using Metaheuristic Evolutionary Algorithms.
Circuits Syst. Signal Process., May, 2023

Generation of Non-Linear Technique Based 6 Hourly Wind Reanalysis Products Using SCATSAT-1 and Numerical Weather Prediction Model Outputs.
Remote. Sens., February, 2023

A Fractional-Order Meminductor Emulator Using OTA and CDBA with Application in Adaptive Learning Circuit.
Wirel. Pers. Commun., 2023

Refining RNMC compensation for Three Stage Amplifier using DTMOS Transistor and FFVF.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022
DVCC Based (2 + α) Order Low Pass Bessel Filter Using Optimization Techniques.
Wirel. Pers. Commun., 2022

Wideband High Gain Active Feedback Transimpedance Amplifier.
Wirel. Pers. Commun., 2022

Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application.
Integr., 2022

Algorithm to Estimate Scalloping & Banding in Scansar Images and Deep Learning Based Descalloping Technique.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

2021
Approximation of Fractional-Order Butterworth Filter Using Pole-Placement in W-Plane.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain.
Microelectron. J., 2021

Analysis and Design of Optimized Fractional Order Low-Pass Bessel Filter.
J. Circuits Syst. Comput., 2021

Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications.
J. Circuits Syst. Comput., 2021

2020
Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended
Springer, ISBN: 978-981-15-0981-0, 2020

2019
A closed-loop ASIC design approach based on logical effort theory and artificial neural networks.
Integr., 2019

RISAT-1 SAR HRS Mode Data Quality Evaluation.
Proceedings of the 2019 IEEE International Geoscience and Remote Sensing Symposium, 2019

2018
Comment: Multifunction Current Differencing Cascaded Transconductance Amplifier (MCDTA) and Its Application to Current-Mode Multiphase Sinusoidal Oscillator.
Wirel. Pers. Commun., 2018

Design and Analysis of Tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) with Enhanced Performance and Its Application in Filters.
Wirel. Pers. Commun., 2018

Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms.
Integr., 2018

High bandwidth transimpedance amplifier using FGMOS for low voltage operation.
Integr., 2018

2017
Low-voltage low-power high performance current mode fullwave rectifier.
Microelectron. J., 2017

DTMOS and FD-FVF based low voltage high performance Voltage Differencing Transconductance Amplifier (VDTA) and its application in MISO filter.
Microelectron. J., 2017

2016
A comparative study of various current mirror configurations: Topologies and characteristics.
Microelectron. J., 2016

DTMOS based low voltage high performance FVF-OTA and its application in MISO filter.
Proceedings of the 2016 International Conference on Advances in Computing, 2016

2015
A new wideband regulated cascode amplifier with improved performance and its application.
Microelectron. J., 2015

Low-voltage low-power FGMOS based VDIBA and its application as universal filter.
Microelectron. J., 2015

2014
An efficient triple-tail cell based PFSCL D latch.
Microelectron. J., 2014

The Design of the IIR Differintegrator and its Application in Edge Detection.
J. Inf. Process. Syst., 2014

Wideband digital integrators and differentiators designed using particle swarm optimisation.
IET Signal Process., 2014

2013
High frequency flipped voltage follower with improved performance and its application.
Microelectron. J., 2013

Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells.
Microelectron. J., 2013

Analysis of low voltage bulk-driven self-biased high swing cascode current mirror.
Microelectron. J., 2013

Automated transistor width optimisation algorithms for digital circuits.
Int. J. Embed. Syst., 2013

A low voltage wide swing level shifted FVF based current mirror.
Proceedings of the International Conference on Advances in Computing, 2013

2011
New Approach to Realize Fractional Power in z-Domain at Low Frequency.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Low-voltage FGMOS based analog building blocks.
Microelectron. J., 2011

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic.
J. Electr. Comput. Eng., 2011

Digital fractional-order differentiator and integrator models based on first-order and higher order operators.
Int. J. Circuit Theory Appl., 2011

Recursive wideband digital integrator and differentiator.
Int. J. Circuit Theory Appl., 2011

Realizations of Grounded Negative Capacitance Using CFOAs.
Circuits Syst. Signal Process., 2011

2010
FGMOS based voltage-controlled resistor and its applications.
Microelectron. J., 2010

2009
Low-Voltage Cascode Current Mirror Based on Bulk-Driven MOSFET and FGMOS Techniques.
Proceedings of the ARTCom 2009, 2009

2008
Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models.
Proceedings of the SIGMAP 2008, 2008


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