G. S. Visweswaran
According to our database1,
G. S. Visweswaran
authored at least 27 papers
between 1997 and 2019.
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Bibliography
2019
A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression Scheme.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2018
A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Impact of crosstalk and process variation on capture power reduction for at-speed test.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
2015
A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Digital fractional-order differentiator and integrator models based on first-order and higher order operators.
Int. J. Circuit Theory Appl., 2011
2010
Proceedings of the 18th European Signal Processing Conference, 2010
2008
Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models.
Proceedings of the SIGMAP 2008, 2008
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
2005
A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
2004
Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997