Marcus Jeitler

According to our database1, Marcus Jeitler authored at least 4 papers between 2009 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Enhancing pipelined processor architectures with fast autonomous recovery of transient faults.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection.
Proceedings of the Annual Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2009


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