Andreas Steininger

Orcid: 0000-0002-3847-1647

Affiliations:
  • TU Wien, Vienna, Austria


According to our database1, Andreas Steininger authored at least 136 papers between 1991 and 2023.

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Bibliography

2023
The Hidden Behavior of a D-Latch.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

ISimDL: Importance Sampling-Driven Acceleration of Fault Injection Simulations for Evaluating the Robustness of Deep Learning.
CoRR, 2023

SHIELD: An Adaptive and Lightweight Defense against the Remote Power Side-Channel Attacks on Multi-tenant FPGAs.
CoRR, 2023

On the Susceptibility of QDI Circuits to Transient Faults.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2023

SET Effects on Quasi Delay Insensitive and Synchronous Circuits.
Proceedings of the IEEE European Test Symposium, 2023

Towards Resilient Quasi Delay Insensitive Conditional Control Elements.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

2022
Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons.
CoRR, 2022

enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

Towards Resilient QDI Pipeline Implementations.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

SET Hardened Derivatives of QDI Buffer Template.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

On SAT-Based Model Checking of Speed-Independent Circuits.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020
On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

Timing Domain Crossing using Muller Pipelines.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
An Experimental Study of Metastability-Induced Glitching Behavior.
J. Circuits Syst. Comput., 2019

International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Proceedings of the IEEE International Test Conference, 2019

Sustainable Security & Safety: Challenges and Opportunities.
Proceedings of the 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems, 2019

Efficient Metastability Characterization for Schmitt-Triggers.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
Refined metastability characterization using a time-to-digital converter.
Microelectron. Reliab., 2018

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017
A versatile architecture for long-term monitoring of single-event transient durations.
Microprocess. Microsystems, 2017

Foreword.
J. Circuits Syst. Comput., 2017

A Model for the Metastability Delay of Sequential Elements.
J. Circuits Syst. Comput., 2017

Setup for an Experimental Study of Radiation Effects in 65nm CMOS.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Measuring metastability using a time-to-digital converter.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Measuring Metastability with Free-Running Clocks.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
On the Appropriate Handling of Metastable Voltages in FPGAs.
J. Circuits Syst. Comput., 2016

A new coding scheme for fault tolerant 4-phase delay-insensitive codes.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Study of a delayed single-event effect in the Muller C-element.
Proceedings of the 21th IEEE European Test Symposium, 2016

Design and Physical Implementation of a Target ASIC for SET Experiments.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

A general approach for comparing metastable behavior of digital CMOS gates.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

The Metastable Behavior of a Schmitt-Trigger.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
A composable real-time architecture for replicated railway applications.
J. Syst. Archit., 2015

Building reliable systems-on-chip in nanoscale technologies.
Elektrotech. Informationstechnik, 2015

Digitale Mikroelektronik in Österreich.
Elektrotech. Informationstechnik, 2015

Fault-tolerant Distributed Systems in Hardware.
Bull. EATCS, 2015

A versatile and reliable glitch filter for clocks.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Methods for analysing and improving the fault resilience of delay-insensitive codes.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A pausible clock with crystal oscillator accuracy.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Reliable and Continuous Measurement of SET Pulse Widths.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enhanced Metastability Characterization Based on AC Analysis.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Measuring the Distribution of Metastable Upsets over Time.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Containment of Metastable Voltages in FPGAs.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

How to Synchronize a Pausible Clock to a Reference.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Runtime verification of microcontroller binary code.
Sci. Comput. Program., 2014

Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.
J. Comput. Syst. Sci., 2014

Equivalence of clock gating and synchronization with applicability to GALS communication.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Measuring SET pulsewidths in logic gates using digital infrastructure.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Architecture for monitoring SET propagation in 16-bit Sklansky adder.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Protection of Muller-Pipelines from transient faults.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A tree arbiter cell for high speed resource sharing in asynchronous environments.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
An infrastructure for accurate characterization of single-event transients in digital circuits.
Microprocess. Microsystems, 2013

Software Composability and Mixed Criticality for Triple Modular Redundant Architectures.
Proceedings of the SAFECOMP 2013, 2013

Metastability characterization for muller C-elements.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

SET propagation in micropipelines.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Digital Late-Transition Metastability Simulation Model.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Multi-Credit Flow Control scheme for asynchronous NoCs.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

An Approach for Efficient Metastability Characterization of FPGAs through the Designer.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

An SET Tolerant Tree Arbiter Cell.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs
CoRR, 2012

Muller C-Element Metastability Containment.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Protecting an Asynchronous NoC against Transient Channel Faults.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Radiation-tolerant combinational gates - an implementation based comparison.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Designing FlexRay-based automotive architectures: A holistic OEM approach.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation.
J. Electr. Comput. Eng., 2011

Replicated processors on a single die - How independently do they fail?
Elektrotech. Informationstechnik, 2011

Automated Test-Trace Inspection for Microcontroller Binary Code.
Proceedings of the Runtime Verification - Second International Conference, 2011

Past Time LTL Runtime Verification for Microcontroller Binary Code.
Proceedings of the Formal Methods for Industrial Critical Systems, 2011

2010
Test-Case Generation for Embedded Binary Code Using Abstract Interpretation.
Proceedings of the Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2010

Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

Enhancing pipelined processor architectures with fast autonomous recovery of transient faults.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A deterministic approach for hardware fault injection in asynchronous QDI logic.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach.
IEEE Trans. Ind. Informatics, 2009

Is Asynchronous Logic More Robust Than Synchronous Logic?.
IEEE Trans. Dependable Secur. Comput., 2009

A Metastability-Free Multi-synchronous Communication Scheme for SoCs.
Proceedings of the Stabilization, 2009

Power supply induced common cause faults-experimental assessment of potential countermeasures.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

On the Risk of Fault Coupling over the Chip Substrate.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

On the role of the power supply as an entry for common cause faults - An experimental analysis.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Remote measurement of local oscillator drifts in FlexRay networks.
Proceedings of the Design, Automation and Test in Europe, 2009

On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Towards a Systematic Test for Embedded Automotive Communication Systems.
IEEE Trans. Ind. Informatics, 2008

Flexible Hardware-Based Stereo Matching.
EURASIP J. Embed. Syst., 2008

An investigation of the clique problem in FlexRay.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

Automated generation of explicit connectors for component based hardware/software interaction in embedded real-time systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Error Containment in the Presence of Metastability.
Proceedings of the Fault-Tolerant Distributed Algorithms on VLSI Chips, 07.09., 2008

Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2008

2007
FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung.
Elektrotech. Informationstechnik, 2007

A Fail-Silent Reconfigurable Superscalar Processor.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

The effect of quartz drift on convergence-average based clock synchronization.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

Hardware implementation of an SAD based stereo vision algorithm.
Proceedings of the 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 2007

2006
Automatic Parameter Identi cation in FlexRay based Automotive Communication Networks.
Proceedings of 11th IEEE International Conference on Emerging Technologies and Factory Automation, 2006

A Reconfigurable Generic Dual-Core Architecture.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Recovery Mechanisms for Dual Core Architectures.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

VLSI Implementation of a Fault-Tolerant Distributed Clock Generation.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
A structured approach for the systematic test of embedded automotive communication systems.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Efficient stimulus generation for testing embedded distributed systems the FlexRay example.
Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, 2005

2004
A Generic Dual Core Architecture with Error Containment.
Comput. Artif. Intell., 2004

Embedded Real-Time-Tracer - An Approach with IDE.
Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems, 2004

Built-in Fault Injection in Hardware - The FIDYCO Example.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
A transparent online memory test for simultaneous detection of functional faults and soft errors in memories.
IEEE Trans. Reliab., 2003

Dealing with dormant faults in an embedded fault-tolerant computer system.
IEEE Trans. Reliab., 2003

Built-In Fault Injectors - The Logical Continuation of BIST?
Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems, 2003

Processor Support for Temporal Predictability - The SPEAR Design Example.
Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS 2003), 2003

2002
Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault Injection Experiments.
IEEE Trans. Computers, 2002

Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
How to Tune the MTTF of a Fail-Silent System.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Testing and built-in self-test - A survey.
J. Syst. Archit., 2000

How Does Resource Utilization Affect Fault Tolerance?
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
On the determination of dynamic errors for rise time measurement with an oscilloscope.
IEEE Trans. Instrum. Meas., 1999

Economic Online Self-Test in the Time-Triggered Architecture.
IEEE Des. Test Comput., 1999

On the Necessity of On-Line-BIST in Safety-Critical Applications - A Case Study.
Proceedings of the Digest of Papers: FTCS-29, 1999

1997
On Finding an Optimal Combination of Error Detection Mechanisms Based on Results of Fault Injection Experiments.
Proceedings of the Digest of Papers: FTCS-27, 1997

1995
A Model for the Analysis of the Fault Injection Process.
Proceedings of the Digest of Papers: FTCS-25, 1995

1993
The design of a fail-silent processing node for the predictable hard real-time system MARS.
Distributed Syst. Eng., 1993

1991
Towards an optimal combination of error detection mechanisms.
Microprocessing and Microprogramming, 1991

Can the advantages of RISC be utilized in real time systems?
Proceedings of the Euromicro '91 Workshop on Real Time Systems, 1991


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